AltOr32 - Alternative Lightweight OpenRisc CPU
☆13Dec 17, 2015Updated 10 years ago
Alternatives and similar repositories for altor32
Users that are interested in altor32 are comparing it to the libraries listed below. We may earn a commission when you buy through links labeled 'Ad' on this page.
Sorting:
- 64-bit MISC Architecture CPU☆13Dec 13, 2016Updated 9 years ago
- Multi-threaded 32-bit embedded core family.☆24Jul 9, 2012Updated 14 years ago
- 10_100_1000 Mbps tri-mode ethernet MAC☆11Jul 17, 2014Updated 12 years ago
- openMSP430 CPU core (from OpenCores)☆22Oct 14, 2022Updated 3 years ago
- MMC (and derivative standards) host controller☆26Sep 14, 2020Updated 5 years ago
- Managed Kubernetes at scale on DigitalOcean • AdDigitalOcean Kubernetes includes the control plane, bandwidth allowance, container registry, automatic updates, and more for free.
- Pipelined FFT/IFFT 64 points processor☆11Jul 17, 2014Updated 12 years ago
- Y80e - Z80/Z180 compatible processor extended by eZ80 instructions☆22Jul 17, 2014Updated 12 years ago
- Gaussian noise generator Verilog IP core☆34Jul 5, 2026Updated last month
- Amber ARM-compatible core☆18Jul 17, 2014Updated 12 years ago
- OSCAR main source repository.☆16Sep 25, 2025Updated 10 months ago
- ☆11Dec 6, 2023Updated 2 years ago
- ☆16Dec 18, 2016Updated 9 years ago
- Verilog code of Loongson's GS132 core☆12Dec 19, 2019Updated 6 years ago
- Reed Solomon Encoder and Decoder Digital IP☆22Jun 14, 2020Updated 6 years ago
- GPU virtual machines on DigitalOcean Gradient AI • AdGet to production fast with high-performance AMD and NVIDIA GPUs you can spin up in seconds. The definition of operational simplicity.
- Grazyna the polish irc bot☆11Jul 6, 2022Updated 4 years ago
- AVR CPU Core Implementation in Verilog HDL.☆15Oct 28, 2018Updated 7 years ago
- Arizona State University CSE320☆13Mar 22, 2015Updated 11 years ago
- This repo shows an implementation of an FPGA from RTL to GDS with open Skywater-130 pdk☆39Jun 2, 2021Updated 5 years ago
- Procedurally generated maps for Hex Empire☆12Updated this week
- Synthesis using Synopsys DC and Physical Design flow using Synopsys ICC II, of my RISC-V 5 stage pipelined using 32 nm tech repo☆15Jul 31, 2024Updated 2 years ago
- fpga based nes box☆34Nov 9, 2021Updated 4 years ago
- PID controller☆25Jul 17, 2014Updated 12 years ago
- RTL implementation for Advanced Encryption Standard (AES) in Verilog. Synthesis Done in Synopsys DC.☆10Dec 11, 2020Updated 5 years ago
- Wordpress hosting with auto-scaling - Free Trial Offer • AdFully Managed hosting for WordPress and WooCommerce businesses that need reliable, auto-scalable performance. Cloudways SafeUpdates now available.
- Generic AXI master stub☆20Jul 17, 2014Updated 12 years ago
- A simple low-resource usage Kalman Filter using shared resources - in MyHDL☆10Oct 7, 2024Updated last year
- ☆14Jul 17, 2023Updated 3 years ago
- RPython by Example (RPyBE) is a collection of runnable examples that illustrate various RPython concepts and libraries.☆17May 25, 2022Updated 4 years ago
- Educational 16-bit MIPS Processor☆18Feb 16, 2019Updated 7 years ago
- SHA3 (KECCAK)☆20Jul 17, 2014Updated 12 years ago
- Solving Advent of Code 2017 puzzles in a different language every day☆11Mar 23, 2018Updated 8 years ago
- Verilog IP Cores & Tests☆13May 3, 2018Updated 8 years ago
- ☆20Jul 5, 2026Updated last month
- 1-Click AI Models by DigitalOcean Gradient • AdDeploy popular AI models on DigitalOcean Gradient GPU virtual machines with just a single click. Zero configuration with optimized deployments.
- Verilog CAN controller that is compatible to the SJA 1000.☆19Apr 17, 2021Updated 5 years ago
- ☆10Feb 14, 2026Updated 5 months ago
- ARM-CPU implemented verilog☆30Jan 13, 2024Updated 2 years ago
- RISC-V Soft CPU Security Contest by Thales and Microchip Technology☆12Jul 29, 2019Updated 7 years ago
- Binary Single Precision Floating-point Fused Multiply-Add Unit Design (Verilog HDL)☆22Jul 8, 2013Updated 13 years ago
- Open Source Cell Library for Predictive CNFET Technology☆15Mar 12, 2026Updated 5 months ago
- This paper presents design of UART module for serial communication used for short-distance, low speed and exchange of data between comput…☆15Mar 30, 2022Updated 4 years ago