Alternatives and similar repositories for ChainsawOld:

Users that are interested in ChainsawOld are comparing it to the libraries listed below

• Chainsaw-Team / Chainsaw
  a hardware design library based on SpinalHDL, especially for stream processing operators on Xilinx FPGAs for Arithmetic, DSP, Communicati…
  ☆61Updated last year
• KasuganoSoraaa / simple-AXI2AHB-bridge
  AXI master to AHB slave, support INCR/WRAP, out of standing, do not advanced feature such as support out of order, retry, split, etc
  ☆39Updated 3 years ago
• VenciFreeman / FFT_ChipDesign
  A 16-point radix-4 FFT chip, including Verilog codes, netlists and layout. Group project.
  ☆61Updated 8 months ago
• pulp-platform / axi_spi_master
  ☆21Updated 5 years ago
• abdelrhman-oun / DDR5_PHY_WriteOperation
  ☆50Updated 2 years ago
• amonemi / ProNoC
  Prototype-network-on-chip (ProNoC) is an EDA tool that facilitates prototyping of custom heterogeneous NoC-based many-core-SoC (MCSoC).
  ☆55Updated last month
• freecores / dma_ahb
  AHB DMA 32 / 64 bits
  ☆54Updated 10 years ago
• thuCGRA / SpinalHDL_Chinese_Doc
  Translated SpinalHDL-Doc(v1.7.2) into Chinese
  ☆48Updated last year
• hizbi-github / AXI4_Master_Interconnect_Slave
  A generic implementation of AMBA AXI4 communication protocol. The design provides a master, a slave and an interconnect with multiple mas…
  ☆38Updated 2 years ago
• bakhshalipour / NoC-Verilog
  A verilog implementation for Network-on-Chip
  ☆73Updated 7 years ago
• seonskim / verilog_axi-interconnect
  AXI Interconnect
  ☆47Updated 3 years ago
• ptracton / AXI_BFM
  AXI4 BFM in Verilog
  ☆32Updated 8 years ago
• mmxsrup / axi4-interface
  AXI4 and AXI4-Lite interface definitions
  ☆92Updated 4 years ago
• ljgibbslf / basic_cache_core
  ☆27Updated 4 years ago
• ahmedshahein / DSP-RTL-Lib
  RTL Verilog library for various DSP modules
  ☆86Updated 3 years ago
• FPGA-Networking / Low-Cost-and-Programmable-CRC
  Source code of the paper "Low-Cost and Programmable CRC Implementation based on FPGA"
  ☆42Updated 4 years ago
• adki / DPI_Tutorial
  SystemVerilog Direct Programming Interface (DPI) Tutorial
  ☆58Updated 4 years ago
• aignacio / axi_dma
  General Purpose AXI Direct Memory Access
  ☆49Updated 11 months ago
• IA-C-Lab-Fudan / Chisel-FFT-generator
  FFT generator using Chisel
  ☆58Updated 3 years ago
• Verdvana / AXI4_Interconnect
  AXI总线连接器
  ☆97Updated 5 years ago
• kuladeepsaireddy / OpenNoc
  ☆31Updated 5 years ago
• Lianghao-Yuan / AHB_Bus_Matrix
  ☆36Updated 9 years ago
• funannoka / SoC-Design-DDR3-Controller
  DDR3 SDRAM Memory Controller Design & Synthesis using System Verilog
  ☆31Updated 6 years ago
• pulp-platform / axi_mem_if
  Simple single-port AXI memory interface
  ☆41Updated 10 months ago
• ananthbhat94 / DDR4MemoryController
  HDL code for a DDR4 memory controller implementing an Open Page Policy and Out of Order execution.
  ☆74Updated 7 years ago
• Aperture-Electronic / SystemVerilog-Bitmap-Library-AXI-Image-VIP
  Bitmap Processing Library & AXI-Stream Video Image VIP
  ☆30Updated 3 years ago
• wanderingnail / AXI_DMA
  ☆19Updated 2 years ago
• xiaoerlang0359 / E203plus
  upgrade to e203 (a risc-v core)
  ☆42Updated 4 years ago
• esynr3z / axi_vip_demo
  Xilinx AXI VIP example of use
  ☆38Updated 4 years ago
• ForrestBlue / cortexm0ds
  ☆61Updated 9 years ago