RicardoNid / ChainsawOld
☆23Updated 2 years ago
Alternatives and similar repositories for ChainsawOld:
Users that are interested in ChainsawOld are comparing it to the libraries listed below
- a hardware design library based on SpinalHDL, especially for stream processing operators on Xilinx FPGAs for Arithmetic, DSP, Communicati…☆57Updated last year
- AXI4 BFM in Verilog☆31Updated 8 years ago
- AHB DMA 32 / 64 bits☆52Updated 10 years ago
- ☆16Updated 2 years ago
- Translated SpinalHDL-Doc(v1.7.2) into Chinese☆48Updated last year
- ☆20Updated 5 years ago
- A generic implementation of AMBA AXI4 communication protocol. The design provides a master, a slave and an interconnect with multiple mas…☆30Updated 2 years ago
- SystemVerilog Direct Programming Interface (DPI) Tutorial☆45Updated 4 years ago
- ☆35Updated 9 years ago
- AXI Interconnect☆47Updated 3 years ago
- AXI master to AHB slave, support INCR/WRAP, out of standing, do not advanced feature such as support out of order, retry, split, etc☆36Updated 2 years ago
- commit rtl and build cosim env☆13Updated 11 months ago
- ☆37Updated 2 years ago
- AXI DMA 32 / 64 bits☆103Updated 10 years ago
- FFT generator using Chisel☆57Updated 3 years ago
- an open source uvm verification platform for e200 (riscv)☆26Updated 6 years ago
- ☆26Updated 5 years ago
- General Purpose AXI Direct Memory Access☆48Updated 8 months ago
- System Verilog and Emulation. Written all the five channels.☆32Updated 7 years ago
- AXI3 Bus Functional Models (Initiator & Target)☆27Updated 2 years ago
- Use ORDT and systemRDL tools to generate C/Verilog header files, register RTL, UVM register models, and docs from compiled SystemRDL.☆66Updated 5 years ago
- UVM Testbench For SystemVerilog Combinator Implementation☆53Updated 7 years ago
- AXI4 and AXI4-Lite interface definitions☆88Updated 4 years ago
- AXI总线连接器☆93Updated 4 years ago
- RTL Verilog library for various DSP modules☆84Updated 2 years ago
- ☆25Updated 4 years ago
- HDLGen is an HDL generation tool, supporting embedded Perl or Python script, reduce manual work & improve effiency with a few embedded f…☆88Updated last year
- AHB3-Lite Interconnect☆83Updated 8 months ago
- A 16-point radix-4 FFT chip, including Verilog codes, netlists and layout. Group project.☆56Updated 5 months ago
- UVM register utility generation by inputting xls table☆35Updated last year