☆23Oct 1, 2022Updated 3 years ago
Alternatives and similar repositories for ChainsawOld
Users that are interested in ChainsawOld are comparing it to the libraries listed below. We may earn a commission when you buy through links labeled 'Ad' on this page.
Sorting:
- A Hardware Implemented Poseidon Hasher☆20Apr 15, 2022Updated 3 years ago
- AdderNet ResNet20 for cifar10 written in SpinalHDL☆35Mar 14, 2021Updated 5 years ago
- ☆10Jan 25, 2023Updated 3 years ago
- Translate the source code of Veriog version to Spinalhdl version☆10Jul 1, 2021Updated 4 years ago
- SpinalHDL - Cryptography libraries☆59Jul 19, 2024Updated last year
- 1-Click AI Models by DigitalOcean Gradient • AdDeploy popular AI models on DigitalOcean Gradient GPU virtual machines with just a single click and start building anything your business needs.
- The hardware implementation of Poseidon hash function in SpinalHDL☆21Jun 5, 2022Updated 3 years ago
- BFM Tester for Chisel HDL☆14Nov 27, 2021Updated 4 years ago
- RISC-V CPU in SystemVerilog & Custom Migen-based SoC Generator☆10Dec 29, 2021Updated 4 years ago
- Demo Sources for Learning Spinal HDL☆16Dec 5, 2022Updated 3 years ago
- SpinalHDL USB system for the ULPI based Arrow DECA board☆20Jan 9, 2022Updated 4 years ago
- Wrapper for ETH Ariane Core☆22Sep 2, 2025Updated 6 months ago
- SpinalHDL based, FPGA Suitable RTL Implementation of RISC-V RV32. Aligned with RISC-V Virtual Prototype☆53Feb 2, 2026Updated last month
- a hardware design library based on SpinalHDL, especially for stream processing operators on Xilinx FPGAs for Arithmetic, DSP, Communicati…☆68Jan 8, 2024Updated 2 years ago
- ☆23Apr 14, 2023Updated 2 years ago
- Managed Database hosting by DigitalOcean • AdPostgreSQL, MySQL, MongoDB, Kafka, Valkey, and OpenSearch available. Automatically scale up storage and focus on building your apps.
- SpinalHDL AdderNet MNIST☆11Feb 26, 2021Updated 5 years ago
- An implementation of the Sodor 1-Stage RISC-V processor in SpinalHDL.☆14Jun 5, 2019Updated 6 years ago
- A simple AXI4 DMA unit written in SpinalHDL.☆18Apr 18, 2020Updated 5 years ago
- A library to retrieve JEP106 manufacturer strings in Rust.☆12May 7, 2025Updated 10 months ago
- This is a personal archive. Please refer to github.com/UCLA-VAST/RapidStream☆15May 31, 2022Updated 3 years ago
- SpinalHDL-tutorial based on Jupyter Notebook☆152Jun 14, 2024Updated last year
- shdl6800: A 6800 processor written in SpinalHDL☆25Jan 12, 2020Updated 6 years ago
- UVM register utility generation by inputting xls table☆39Aug 22, 2023Updated 2 years ago
- RISC-V Rocket Chip Strap-on-Booster with Fused Universal Neural Network (FuNN) eNNgine☆21Mar 17, 2022Updated 4 years ago
- Wordpress hosting with auto-scaling on Cloudways • AdFully Managed hosting built for WordPress-powered businesses that need reliable, auto-scalable hosting. Cloudways SafeUpdates now available.
- ☆10Oct 15, 2021Updated 4 years ago
- This is an SoC design dedicated to Keyword Spotting (KWS) based on a neural-network accelerator and the wujian100 platform.☆54Aug 29, 2020Updated 5 years ago
- A Hardware Construct Language☆44Jul 25, 2022Updated 3 years ago
- ☆17Apr 7, 2022Updated 3 years ago
- Embedded Microprocessor System Design using FPGAs 1. edition ISBN:☆13Apr 1, 2025Updated 11 months ago
- CNN accelerator implemented with Spinal HDL☆18Dec 27, 2021Updated 4 years ago
- This repository contains source code for CNN layers of ALexNet using Xilinx HLS Vivado.☆10Jun 25, 2022Updated 3 years ago
- Xilinx PCIe to MIG DDR4 example designs and custom part data files☆40Feb 4, 2024Updated 2 years ago
- ☆43Mar 18, 2026Updated last week
- Open source password manager - Proton Pass • AdSecurely store, share, and autofill your credentials with Proton Pass, the end-to-end encrypted password manager trusted by millions.
- Rapid Abstraction FPGA Toolbox - Python toolbox which provides direct access to FPGA hardware peripherals☆28Feb 17, 2026Updated last month
- Scala based HDL☆1,952Updated this week
- Scripts for XiangShan☆17Updated this week
- This is a multi-core processor specially designed for matrix multiplication using Verilog HDL.☆11Jan 8, 2022Updated 4 years ago
- commit rtl and build cosim env☆15Feb 15, 2024Updated 2 years ago
- Cocotb (Python) based USB 1.1 test suite for FPGA IP, with testbenches for a variety of open source USB cores☆53Aug 7, 2023Updated 2 years ago
- ☆13Dec 10, 2022Updated 3 years ago