RicardoNid / ChainsawOld
☆23Updated 2 years ago
Alternatives and similar repositories for ChainsawOld:
Users that are interested in ChainsawOld are comparing it to the libraries listed below
- a hardware design library based on SpinalHDL, especially for stream processing operators on Xilinx FPGAs for Arithmetic, DSP, Communicati…☆58Updated last year
- ☆20Updated 5 years ago
- AXI4 BFM in Verilog☆31Updated 8 years ago
- FFT generator using Chisel☆57Updated 3 years ago
- AHB DMA 32 / 64 bits☆52Updated 10 years ago
- Translated SpinalHDL-Doc(v1.7.2) into Chinese☆48Updated last year
- Prototype-network-on-chip (ProNoC) is an EDA tool that facilitates prototyping of custom heterogeneous NoC-based many-core-SoC (MCSoC).☆50Updated this week
- RTL Verilog library for various DSP modules☆84Updated 3 years ago
- General Purpose AXI Direct Memory Access☆48Updated 9 months ago
- AXI4 and AXI4-Lite interface definitions☆92Updated 4 years ago
- AXI master to AHB slave, support INCR/WRAP, out of standing, do not advanced feature such as support out of order, retry, split, etc☆36Updated 2 years ago
- A 16-point radix-4 FFT chip, including Verilog codes, netlists and layout. Group project.☆58Updated 6 months ago
- Source code of the paper "Low-Cost and Programmable CRC Implementation based on FPGA"☆42Updated 4 years ago
- AXI Interconnect☆47Updated 3 years ago
- SystemVerilog Direct Programming Interface (DPI) Tutorial☆45Updated 4 years ago
- DOULOS Easier UVM Code Generator☆31Updated 7 years ago
- AXI3 Bus Functional Models (Initiator & Target)☆28Updated 2 years ago
- For pre-silicon developers of RISC-V systems, riscv-vip is a SystemVerilog project that helps with pre-si verification and debug☆58Updated 4 years ago
- ☆29Updated 5 years ago
- INT8 & FP16 multiplier accumulator (MAC) design with UVM verification completed.☆88Updated 4 years ago
- AXI总线连接器☆94Updated 4 years ago
- Some useful documents of Synopsys☆62Updated 3 years ago
- System Verilog and Emulation. Written all the five channels.☆32Updated 7 years ago
- AXI DMA 32 / 64 bits☆106Updated 10 years ago
- HDLGen is an HDL generation tool, supporting embedded Perl or Python script, reduce manual work & improve effiency with a few embedded f…☆88Updated last year
- DDR5 PHY Graduation project (Verification Team) under supervision of Si-Vision☆43Updated 11 months ago
- A look ahead, round-robing parametrized arbiter written in Verilog.☆42Updated 4 years ago
- HDL code for a DDR4 memory controller implementing an Open Page Policy and Out of Order execution.☆73Updated 6 years ago
- ☆25Updated 4 years ago
- round robin arbiter☆70Updated 10 years ago