Alternatives and similar repositories for 6th-AI-Edge-Contest

Users that are interested in 6th-AI-Edge-Contest are comparing it to the libraries listed below

• briansune / Kintex-7-OV13850-Verilog
  kintex7 ov13850 fpga mipi camera
  ☆20Updated last month
• halftop / Interface-Protocol-in-Verilog
  Interface Protocol in Verilog
  ☆51Updated 6 years ago
• damdoy / fpga_image_processing
  IP operations in verilog (simulation and implementation on ice40)
  ☆62Updated 6 years ago
• DeamonYang / FPGA_FFT
  基于FPGA的FFT
  ☆19Updated 6 years ago
• Anthon1e / JESD204B-Transport-and-Data-Link-Layer
  Implementation of JESD204B Transport Layer & part of Data Link Layer
  ☆39Updated 4 years ago
• uwemeyerbaese / DSP_with_FPGAs_ed4
  DSP with FPGAs 4. edition ISBN: 978-3-642-45308-3
  ☆76Updated 2 months ago
• WangXuan95 / FPGA-HDMI
  An FPGA-based HDMI display controller. 基于FPGA的HDMI显示控制器
  ☆86Updated last year
• hellgate202 / csi2_rx
  MIPI CSI-2 RX
  ☆37Updated 4 years ago
• ajackevic / ELEC5882
  The Design and Implementation of a Pulse Compression Filter on an FPGA.
  ☆32Updated 4 years ago
• cjhonlyone / ADC-lvds
  Xilinx FPGA, ADC344X, AD9252, 14x 12x Serdes, LVDS
  ☆60Updated 3 years ago
• sh-vlad / FPGA_rtime_HDR_video
  We are aimed at making a device for shooting real-time HDR (High Dynamic Range) video using FPGA.
  ☆31Updated 6 years ago
• ahmedshahein / DSP-RTL-Lib
  RTL Verilog library for various DSP modules
  ☆93Updated 3 years ago
• funannoka / SoC-Design-DDR3-Controller
  DDR3 SDRAM Memory Controller Design & Synthesis using System Verilog
  ☆32Updated 7 years ago
• DexWen / LMS-Adaptive-filter
  LMS-Adaptive Filter implement using verilog and Matlab
  ☆48Updated 9 years ago
• RedFlag2017 / rs-codec
  Reed Solomon Encoder and Decoder Digital IP
  ☆21Updated 5 years ago
• vladniculescu / High-Speed-FPGA-based-Data-Acquisition-System-100MSPS
  ☆19Updated 2 years ago
• echoPinkApple / bilinear
  Bilinear interpolation realizes image scaling based on FPGA
  ☆29Updated 5 years ago
• alknvl / axis_udp
  This repository contains simple implementation of UDP/IP stack with 64-bit AXI-Stream interface. ICMP and ARP requests are partially supp…
  ☆63Updated 3 years ago
• jomonkjoy / Tool-Make-Script
  Synopsys Design compiler, VCS and Tetra-MAX
  ☆19Updated 7 years ago
• westonb / OV7670-Verilog
  Verilog modules required to get the OV7670 camera working
  ☆77Updated 7 years ago
• Heng-xiu / implement-CRC-32-in-Verilog
  Project in Course named DESIGN AND IMPLEMENTATION OF COMMUNICATION PROTOCOLS in FCU
  ☆14Updated 11 years ago
• hkhajanchi / fpga-pid
  Verilog Modules for a Digital PI Controller implemented on a Digilent NEXYS 4-DDR FPGA
  ☆32Updated 5 years ago
• brown9804 / PCIe-Physical-Layer
  Implementation of the PCIe physical layer
  ☆60Updated 6 months ago
• WangXuan95 / FPGA-QOI
  An FPGA-based QOI image compressor and decompressor in Verilog. 基于FPGA的QOI图像压缩器和解压器。
  ☆37Updated last year
• ZipCPU / dpll
  A collection of phase locked loop (PLL) related projects
  ☆115Updated 2 years ago
• tsnlab / npu
  ☆23Updated last year
• ykqiu / image-processing
  Real-Time Image Processing for ASIC/FGPA
  ☆21Updated 3 years ago
• freecores / verilog_cordic_core
  configurable cordic core in verilog
  ☆53Updated 11 years ago
• louisliuwei / FPGA-Design-Flow-using-Vivado
  This course gives an introduction to digital design tool flow in Xilinx programmable devices using Vivado® Design software suite
  ☆41Updated 6 years ago
• Elrori / Delta-sigma-ADC-verilog
  Delta-sigma ADC,PDM audio FPGA Implementation
  ☆73Updated 3 years ago