Matrix Multiply and Accumulate unit written in System Verilog
☆13Feb 7, 2019Updated 7 years ago
Alternatives and similar repositories for Matrix-MAC-Unit
Users that are interested in Matrix-MAC-Unit are comparing it to the libraries listed below. We may earn a commission when you buy through links labeled 'Ad' on this page.
Sorting:
- A configurable general purpose graphics processing unit for☆12May 18, 2019Updated 6 years ago
- Common SystemVerilog RTL modules for RgGen☆16Feb 5, 2026Updated 2 months ago
- Converting systemverilog to verilog.☆10Feb 15, 2018Updated 8 years ago
- Superscalar Out-of-Order NPU Design on FPGA☆13May 17, 2024Updated last year
- UltraZed Edition examples☆12Oct 29, 2017Updated 8 years ago
- Wordpress hosting with auto-scaling - Free Trial • AdFully Managed hosting for WordPress and WooCommerce businesses that need reliable, auto-scalable performance. Cloudways SafeUpdates now available.
- RISC-V Rocket Chip Strap-on-Booster with Fused Universal Neural Network (FuNN) eNNgine☆21Mar 17, 2022Updated 4 years ago
- Integration test for entire CGRA flow☆12Jan 17, 2020Updated 6 years ago
- A risc v based architecture to develop a core/ processor which is capable of Matrix MAC Operations☆11Apr 21, 2024Updated last year
- A tiniest ASIC GPU that can render only two texture mapped triangles☆27Jan 2, 2026Updated 3 months ago
- Open NPU is an open-source project dedicated to creating a flexible, extensible, and high-performance neural processing unit (NPU) archit…☆18Jun 20, 2024Updated last year
- ☆20Dec 22, 2025Updated 3 months ago
- ☆14Updated this week
- An open source 3GPP LTE implementation. (GitHub import of https://sourceforge.net/projects/openlte/)☆10Mar 7, 2017Updated 9 years ago
- RL-Pruner: Structured Pruning Using Reinforcement Learning for CNN Compression and Acceleration☆27Jun 8, 2025Updated 10 months ago
- Bare Metal GPUs on DigitalOcean Gradient AI • AdPurpose-built for serious AI teams training foundational models, running large-scale inference, and pushing the boundaries of what's possible.
- Transactional Verilog design and Verilator Testbench for a RISC-V TensorCore Vector co-processor for reproducible linear algebra☆63Dec 19, 2021Updated 4 years ago
- Soft-microcontroller implementation of an ARM Cortex-M0☆30Apr 23, 2019Updated 6 years ago
- ☆82Feb 7, 2025Updated last year
- Reusable image processing modules in SystemVerilog☆33Aug 7, 2017Updated 8 years ago
- ☆18Dec 20, 2023Updated 2 years ago
- An automatic place-and-route tool for Minecraft redstone circuits☆25Apr 1, 2016Updated 10 years ago
- RV32I Single Cycle Processor (CPU)☆12Nov 14, 2021Updated 4 years ago
- Official implementation of ICML'24 paper "LQER: Low-Rank Quantization Error Reconstruction for LLMs"☆19Jul 11, 2024Updated last year
- ☆35Mar 1, 2019Updated 7 years ago
- Serverless GPU API endpoints on Runpod - Bonus Credits • AdSkip the infrastructure headaches. Auto-scaling, pay-as-you-go, no-ops approach lets you focus on innovating your application.
- Matrix Accelerator Generator for GeMM Operations based on SIGMA Architecture in CHISEL HDL☆15Mar 21, 2024Updated 2 years ago
- System verilog register model for uvm testbenches.☆21Aug 29, 2018Updated 7 years ago
- EC499: Major Project☆10Jun 25, 2023Updated 2 years ago
- ☆10Nov 8, 2019Updated 6 years ago
- ☆15Jun 7, 2022Updated 3 years ago
- ☆20Nov 23, 2022Updated 3 years ago
- Digital IC design and vlsi notes☆13Jun 24, 2020Updated 5 years ago
- NuMaker UNO board package for Arduino IDE☆13Nov 26, 2025Updated 4 months ago
- IC implementation of TPU☆150Dec 18, 2019Updated 6 years ago
- Wordpress hosting with auto-scaling - Free Trial • AdFully Managed hosting for WordPress and WooCommerce businesses that need reliable, auto-scalable performance. Cloudways SafeUpdates now available.
- This repository contains simulation files and other relevant files on the On-chip clock multiplier (PLL) (Fclkin—5MHz to 12MHz, Fclkout—4…☆15Oct 18, 2021Updated 4 years ago
- A series of simulations organized as homework assignments that were part of the course on Neuromorphic Engineering at IIT Bombay (course …☆10Jul 19, 2016Updated 9 years ago
- ☆18May 5, 2022Updated 3 years ago
- Vector processor for RISC-V vector ISA☆139Oct 19, 2020Updated 5 years ago
- ELVE : ELVE Logic Visualization Engine☆11Jul 2, 2017Updated 8 years ago
- SRAM macros created for the GF180MCU provided by GlobalFoundries.☆20Apr 10, 2023Updated 3 years ago
- A barebones 64-bit RISC-V micro-controller class CPU, implementing the I(nteger), M(ul/div), C(ompressed) and K(ryptography) extensions.☆48Jan 31, 2022Updated 4 years ago