AleksandarKostovic / Matrix-MAC-UnitLinks
Matrix Multiply and Accumulate unit written in System Verilog
☆12Updated 6 years ago
Alternatives and similar repositories for Matrix-MAC-Unit
Users that are interested in Matrix-MAC-Unit are comparing it to the libraries listed below
Sorting:
- SAURIA (Systolic-Array tensor Unit for aRtificial Intelligence Acceleration) is an open-source Convolutional Neural Network accelerator b…☆64Updated last week
- The Verilog source code for DRUM approximate multiplier.☆31Updated 2 years ago
- SRAM☆22Updated 5 years ago
- ☆27Updated 6 years ago
- Introductory examples for using PYNQ with Alveo☆52Updated 2 years ago
- ☆37Updated 6 years ago
- Educational verilog library that supports IEEE754 floating point arithmetic with a parametrizable mantissa and exponent☆29Updated 7 months ago
- PYNQ Composabe Overlays☆73Updated last year
- Simple examples for FPGA design using Vivado HLS for high level synthesis and Vivado for bitstream generation.☆31Updated 5 years ago
- Accelerating the AES algorithm on an FPGA and comparing the speedup with both AES and Modified AES algorithms☆31Updated 3 years ago
- Design of 1024x32 SRAM (32Kbits) using OpenRAM and SKY130 PDKs with operating voltage of 1.8V and access time < 2.5ns☆79Updated 4 years ago
- An Open Workflow to Build Custom SoCs and run Deep Models at the Edge☆96Updated this week
- 16-bit Adder Multiplier hardware on Digilent Basys 3☆82Updated 2 years ago
- IPs for data-plane integration of Hardware Processing Engines (HWPEs) within a PULP system☆20Updated last week
- EE 260 Winter 2017: Advanced VLSI Design☆66Updated 8 years ago
- 55nm CMOS Open Source PDK by ICsprout Integrated Circuit Co., Ltd.☆66Updated this week
- SoCGen is a tool that automates SoC design by taking in a JSON description of the system and producing the final GDS-II. SoCGen supports …☆39Updated 4 years ago
- CHIPKIT: An agile, reusable open-source framework for rapid test chip development☆42Updated 5 years ago
- RPHAX provides a quick automation flow to develop and prototype hardware accelerators on Xilinx FPGAs. Currently, the framework has suppo…☆20Updated 2 years ago
- 100DaysofRTL & System Verilog design: basic logic gates, mux, half/full subtractor, Encoder, D flipflop, 8 bit counter, LFSR, Custom Coun…☆36Updated 2 years ago
- 32 - bit floating point Multiplier Accumulator Unit (MAC)☆31Updated 4 years ago
- Prototype-network-on-chip (ProNoC) is an EDA tool that facilitates prototyping of custom heterogeneous NoC-based many-core-SoC (MCSoC).☆59Updated last week
- This project is done in the course of "Advanced Physical Design using OpenLANE/Sky130" workshop by VLSI System Design Corporation. In thi…☆51Updated 4 years ago
- This is a tutorial on standard digital design flow☆79Updated 4 years ago
- Digital Hardware Modelling using VHDL, Verilog, SystemVerilog, SystemC, HLS(C++, OpenCL)☆67Updated 8 months ago
- Xilinx AXI VIP example of use☆42Updated 4 years ago
- RISC-V Rocket Chip Strap-on-Booster with Fused Universal Neural Network (FuNN) eNNgine☆21Updated 3 years ago
- NoC (Network-on-Chip) generator that generates Verilog HDL model of NoC consisting of on-chip routers☆67Updated 5 years ago
- 128KB AXI cache (32-bit in, 256-bit out)☆53Updated 4 years ago
- Implementing Different Adder Structures in Verilog☆75Updated 6 years ago