Modular Multi-ported SRAM-based Memory
☆33Nov 8, 2024Updated last year
Alternatives and similar repositories for Multiported-RAM
Users that are interested in Multiported-RAM are comparing it to the libraries listed below. We may earn a commission when you buy through links labeled 'Ad' on this page.
Sorting:
- Switched SRAM-based Multi-ported RAM☆19Nov 10, 2024Updated last year
- Parametric Binary to BCD Converter Using Double Dabble / Shift and Add 3 Algorithm☆16May 28, 2015Updated 11 years ago
- Modular SRAM-based 2D hierarchical-search Binary Content Addressable Memory (2D-BCAM)☆23Nov 10, 2024Updated last year
- RISC-V Rocket Chip Strap-on-Booster with Fused Universal Neural Network (FuNN) eNNgine☆21Mar 17, 2022Updated 4 years ago
- This is the repository containing the implementation of sparse dense matrix multiplication for the matrix dimension of 560 x 560.☆10Jul 7, 2021Updated 5 years ago
- Wordpress hosting with auto-scaling - Free Trial Offer • AdFully Managed hosting for WordPress and WooCommerce businesses that need reliable, auto-scalable performance. Cloudways SafeUpdates now available.
- Multi-port BRAM IP for ASIC and FPGA☆14Apr 21, 2021Updated 5 years ago
- ☆17Apr 7, 2026Updated 6 months ago
- SHA-256 cipher algorithm implementation☆13Jun 22, 2025Updated last year
- ☆35Dec 24, 2015Updated 10 years ago
- Implementation of paper "GraphACT: Accelerating GCN Training on CPU-FPGA Heterogeneous Platform".☆12Jun 25, 2020Updated 6 years ago
- ☆21Jun 25, 2025Updated last year
- CATCH 1.0, Initial full release of CATCH cost model.☆21Mar 3, 2026Updated 7 months ago
- Simple single-port AXI memory interface☆51Jun 7, 2024Updated 2 years ago
- Implementation of a circular queue in hardware using verilog.☆18Mar 22, 2019Updated 7 years ago
- Deploy on Railway without the complexity - Free Credits Offer • AdConnect your repo and Railway handles the rest with instant previews. Quickly provision container image services, databases, and storage volumes.
- Alpha64 R10000 Two-Way Superscalar Processor☆12May 6, 2019Updated 7 years ago
- A set of standalone kernel modules and userspace library for using the AXI DMA on a Zynq MPSoC☆22Feb 22, 2020Updated 6 years ago
- FPGA_PCIe_drivers☆16Sep 3, 2015Updated 11 years ago
- ☆18Jul 12, 2024Updated 2 years ago
- TLCS-90 ROM Reader☆15Jul 11, 2026Updated 3 months ago
- Open-source NPU (Neural Processing Unit) for LLM inference - runs GPT-2, LLaMA, Mistral, Qwen2☆12Mar 15, 2026Updated 7 months ago
- HYF's high quality verilog codes☆19Dec 25, 2024Updated last year
- DaCH: dataflow cache for high-level synthesis.☆20Jul 27, 2023Updated 3 years ago
- This is a 4*5 PE array for LeNet accelerator based on FPGA.☆13Jul 20, 2022Updated 4 years ago
- Deploy on Railway without the complexity - Free Credits Offer • AdConnect your repo and Railway handles the rest with instant previews. Quickly provision container image services, databases, and storage volumes.
- RTL implementation of a performance/area optimized bfloat16 adder and multiplication.☆39Mar 28, 2026Updated 7 months ago
- Repository for Xilinx PCIe DMA drivers☆45Jan 19, 2018Updated 8 years ago
- SoftCPU/SoC engine-V☆56Apr 28, 2026Updated 6 months ago
- VCD file viewer for Neovim☆15Feb 20, 2022Updated 4 years ago
- A RISC-V CPU implementation☆17Apr 9, 2020Updated 6 years ago
- Python library for parsing module definitions and instantiations from SystemVerilog files☆27Apr 29, 2021Updated 5 years ago
- Xilinx AR65444 - Xilinx PCIe DMA Driver for linux☆22May 10, 2019Updated 7 years ago
- A parser for PTX 6.5☆13Jun 19, 2023Updated 3 years ago
- An RTL generator for a last-level shared inclusive TileLink cache controller☆27Aug 8, 2026Updated 2 months ago
- Managed Kubernetes at scale on DigitalOcean • AdDigitalOcean Kubernetes includes the control plane, bandwidth allowance, container registry, automatic updates, and more for free.
- This work implements a dynamic programming algorithm for performing local sequence alignment. Through parallelism, it can run 136X times …☆28Jul 4, 2019Updated 7 years ago
- hardware library for hwt (= ipcore repo)☆45Oct 17, 2026Updated 2 weeks ago
- A Python module to interact with an Intel JTAG UART☆17May 8, 2021Updated 5 years ago
- whatever it means☆19Jun 10, 2026Updated 4 months ago
- LEGO is a compiler-agnostic framework for algebraic memory layout specification and transformation, enabling high-performance kernels acr…☆13Sep 17, 2026Updated last month
- Colorspace conversion, gamma correction, and more -- all integrated within a MIPI-to-HDMI pipeline in FPGA.☆35Jul 30, 2020Updated 6 years ago
- [UNRELEASED] FP div/sqrt unit for transprecision☆28Jul 27, 2026Updated 3 months ago