AmeerAbdelhadi / Multiported-RAMLinks
Modular Multi-ported SRAM-based Memory
☆30Updated 8 months ago
Alternatives and similar repositories for Multiported-RAM
Users that are interested in Multiported-RAM are comparing it to the libraries listed below
Sorting:
- Xilinx AXI VIP example of use☆41Updated 4 years ago
- Examples for creating AXI-interfaced peripherals in Chisel☆77Updated 9 years ago
- ☆97Updated last year
- Simple single-port AXI memory interface☆44Updated last year
- Platform Level Interrupt Controller☆41Updated last year
- SystemVerilog Direct Programming Interface (DPI) Tutorial☆66Updated 4 years ago
- RTL sources of the High-Performance L1 Dcache (HPDcache) for OpenHW CV cores☆87Updated this week
- SystemVerilog modules and classes commonly used for verification☆50Updated 6 months ago
- AutoSVA is a tool to automatically generate formal testbenches for unit-level RTL verification. The goal is to, based on annotations made…☆85Updated last year
- Prototype-network-on-chip (ProNoC) is an EDA tool that facilitates prototyping of custom heterogeneous NoC-based many-core-SoC (MCSoC).☆58Updated this week
- IEEE 754 single and double precision floating point library in systemverilog and vhdl☆67Updated 7 months ago
- ☆51Updated 6 years ago
- NoC (Network-on-Chip) generator that generates Verilog HDL model of NoC consisting of on-chip routers☆66Updated 5 years ago
- General Purpose AXI Direct Memory Access☆54Updated last year
- A Style Guide for the Chisel Hardware Construction Language☆108Updated 4 years ago
- RISC-V Verification Interface☆98Updated last month
- Project repo for the POSH on-chip network generator☆48Updated 4 months ago
- Introductory course into static timing analysis (STA).☆95Updated 2 weeks ago
- Advanced Architecture Labs with CVA6☆65Updated last year
- A Fast, Low-Overhead On-chip Network☆214Updated this week
- A barebones 64-bit RISC-V micro-controller class CPU, implementing the I(nteger), M(ul/div), C(ompressed) and K(ryptography) extensions.☆45Updated 3 years ago
- Open source RTL simulation acceleration on commodity hardware☆28Updated 2 years ago
- ☆30Updated 2 weeks ago
- a hardware design library based on SpinalHDL, especially for stream processing operators on Xilinx FPGAs for Arithmetic, DSP, Communicati…☆64Updated last year
- A dynamic verification library for Chisel.☆153Updated 8 months ago
- Universal Verification Methodology (UVM) base libraries, with edits for Verilator☆27Updated 5 years ago
- RaveNoC is a configurable HDL NoC (Network-On-Chip) suitable for MPSoCs and different MP applications☆170Updated 8 months ago
- This repository is dedicated to providing a comprehensive guide and practical examples for using VC Formal for formal verification. Our g…☆34Updated last year
- This is a tutorial on standard digital design flow☆78Updated 4 years ago
- ☆25Updated last year