felsabbagh3 / VortexLinks
RISC-V GPGPU
☆35Updated 5 years ago
Alternatives and similar repositories for Vortex
Users that are interested in Vortex are comparing it to the libraries listed below
Sorting:
- ⛔ DEPRECATED ⛔ RISC-V manycore accelerator for HERO, bigPULP hardware platform☆50Updated 3 years ago
- C/Assembly macros for talking with Rocket Custom Coprocessors (RoCCs)☆53Updated 5 years ago
- Experiments with fixed function renderers and Chisel HDL☆59Updated 6 years ago
- A fault-injection framework using Chisel and FIRRTL☆36Updated last month
- Synthesisable SIMT-style RISC-V GPGPU☆43Updated 4 months ago
- Quasar 2.0: Chisel equivalent of SweRV-EL2☆31Updated 4 years ago
- Top-Level Project for Firebox SoC, consisting of Rocket, BOOM, and peripherals (e.g. Ethernet NIC). This is the default target generator …☆57Updated 5 years ago
- Original RISC-V 1.0 implementation. Not supported.☆42Updated 7 years ago
- A reconfigurable and extensible VLIW processor implemented in VHDL☆36Updated 10 years ago
- Lake is a framework for generating synthesizable memory modules from a high-level behavioral specification and widely-available memory ma…☆22Updated last week
- Based on Chisel3, Rift2Core is a 9-stage, out-of-order, 64-bits RISC-V Core, which supports RV64GC.☆39Updated last year
- Open source fpga project leveraging vtr CAD flow.☆26Updated 2 years ago
- Template for projects using the Hwacha data-parallel accelerator☆34Updated 5 years ago
- FGPU is a soft GPU architecture general purpose computing☆60Updated 5 years ago
- SoftCPU/SoC engine-V☆55Updated 7 months ago
- Instruction set simulator for RISC-V, MIPS and ARM-v6m☆102Updated 4 years ago
- CHIPKIT: An agile, reusable open-source framework for rapid test chip development☆42Updated 5 years ago
- ☆32Updated 2 years ago
- SCARV: a side-channel hardened RISC-V platform☆27Updated 2 years ago
- FPGA reference design for the the Swerv EH1 Core☆72Updated 5 years ago
- Pulp virtual platform☆24Updated 3 months ago
- Z-scale Microarchitectural Implementation of RV32 ISA☆55Updated 8 years ago
- Benchmarks for Yosys development☆24Updated 5 years ago
- OmniXtend cache coherence protocol☆82Updated 5 months ago
- ☆63Updated 6 years ago
- Xilinx Unisim Library in Verilog☆86Updated 5 years ago
- Demo SoC for SiliconCompiler.☆62Updated 2 weeks ago
- ☆61Updated 4 years ago
- REAPR (Reconfigurable Engine for Automata Processing) is a general-purpose framework for accelerating automata processing applications su…☆16Updated 6 years ago
- ☆87Updated this week