felsabbagh3 / VortexLinks
RISC-V GPGPU
☆34Updated 5 years ago
Alternatives and similar repositories for Vortex
Users that are interested in Vortex are comparing it to the libraries listed below
Sorting:
- Template for projects using the Hwacha data-parallel accelerator☆34Updated 4 years ago
- Lake is a framework for generating synthesizable memory modules from a high-level behavioral specification and widely-available memory ma…☆22Updated last week
- Top-Level Project for Firebox SoC, consisting of Rocket, BOOM, and peripherals (e.g. Ethernet NIC). This is the default target generator …☆57Updated 5 years ago
- Experiments with fixed function renderers and Chisel HDL☆59Updated 6 years ago
- C/Assembly macros for talking with Rocket Custom Coprocessors (RoCCs)☆54Updated 4 years ago
- ⛔ DEPRECATED ⛔ RISC-V manycore accelerator for HERO, bigPULP hardware platform☆51Updated 3 years ago
- Custom extensions to the RISC-V isa simulator for the UCB-BAR ESP project☆17Updated 2 years ago
- C++17 implementation of an AST for Verilog code generation☆24Updated last year
- Benchmarks for Yosys development☆24Updated 5 years ago
- A fault-injection framework using Chisel and FIRRTL☆36Updated 3 weeks ago
- A reconfigurable and extensible VLIW processor implemented in VHDL☆32Updated 10 years ago
- FGPU is a soft GPU architecture general purpose computing☆57Updated 4 years ago
- A template for building new projects/platforms using the BOOM core.☆24Updated 6 years ago
- Quasar 2.0: Chisel equivalent of SweRV-EL2☆29Updated 4 years ago
- Original RISC-V 1.0 implementation. Not supported.☆41Updated 6 years ago
- NOCulator is a network-on-chip simulator providing cycle-accurate performance models for a wide variety of networks (mesh, torus, ring, h…☆25Updated 2 years ago
- This is a Clang tool that parses SystemC models, and synthesizes Verilog from it.☆82Updated 7 months ago
- FlexGripPlus: an open-source GPU model for reliability evaluation and micro architectural simulation☆101Updated 2 years ago
- For contributions of Chisel IP to the chisel community.☆61Updated 6 months ago
- The 3rd Iteration of the Berkeley RISC-V DMA Accelerator☆27Updated 5 years ago
- Synthesisable SIMT-style RISC-V GPGPU☆33Updated 2 months ago
- Simple runtime for Pulp platforms☆48Updated 2 weeks ago
- ⛔ DEPRECATED ⛔ HERO Software Development Kit☆20Updated 3 years ago
- Repo for all activity related to the ODSA Bunch of Wires Specification☆24Updated last year
- Home of the specification to connect SemiDynamic's RISC-V cores to your own RISC-V Vector Unit☆36Updated 3 years ago
- ☆61Updated this week
- Pulp virtual platform☆23Updated 2 years ago
- Floating point modules for CHISEL☆32Updated 10 years ago
- SoftCPU/SoC engine-V☆54Updated 2 months ago
- ☆35Updated 10 months ago