jerry-D / HedgeHog-Fused-Spiking-Neural-Network-Emulator-Compute-EngineLinks
HedgeHog Fused Spiking Neural Network Emulator/Compute Engine is a hardware implementation of a SNN designed for implementation in Xilinx Kintex Ultra Plus brand FPGAs and embedded RISC-V as trainer.
☆59Updated 5 months ago
Alternatives and similar repositories for HedgeHog-Fused-Spiking-Neural-Network-Emulator-Compute-Engine
Users that are interested in HedgeHog-Fused-Spiking-Neural-Network-Emulator-Compute-Engine are comparing it to the libraries listed below
Sorting:
- The CyNAPSE Neuromorphic Accelerator: A Digital Spiking neural network accelerator written in fully synthesizable verilog HDL☆34Updated 5 years ago
- Hardware implementation of Spiking Neural Network on a PYNQ-Z1 board☆37Updated 6 years ago
- A repository FPGA-friendly SNN models☆33Updated 4 years ago
- ODIN online-learning digital spiking neural network (SNN) processor - HDL source code and documentation.☆189Updated 6 years ago
- Spiking Neural Network RTL Implementation☆58Updated 4 years ago
- A Spiking Neuron Network Project in Verilog Implementation☆24Updated 7 years ago
- tinyODIN digital spiking neural network (SNN) processor - HDL source code and documentation.☆65Updated 2 years ago
- SNN on FPGA☆10Updated 3 years ago
- ☆19Updated 4 years ago
- CORDIC-SNN, followed with "Unsupervised learning of digital recognition using STDP" published in 2015, frontiers☆23Updated 5 years ago
- [FPL 2021] SyncNN: Evaluating and Accelerating Spiking Neural Networks on FPGAs.☆59Updated 4 years ago
- ☆91Updated 5 years ago
- FPGA acceleration of a Spike-Timing-Dependent Plasticity learning algorithm for Spiking Neural Networks☆38Updated 5 years ago
- This is the RTL implementation of Shenjing, a low power neuromorphic computing accelerator☆17Updated 5 years ago
- Spiking neural network implementation using Verilog with LIF (Leaky Integrate-and-Fire) neurons☆18Updated 5 years ago
- ☆17Updated 4 years ago
- SystemVerilog files for lab project on a DNN hardware accelerator☆16Updated 4 years ago
- FPGA Design of a Spiking Neural Network.☆42Updated last year
- The project includes SRAM In Memory Computing Accelerator with updates in design/circuits submitted previously in MPW7, by IITD researche…☆12Updated 2 years ago
- Systolic array based simple TPU for CNN on PYNQ-Z2☆35Updated 3 years ago
- This project is to design yolo AI accelerator in verilog HDL.☆22Updated 10 months ago
- A three-layer LIF neuron SNN accelerator. The first layer is the input layer and has 784 neurons, that receive the encoded spikes. The se…☆14Updated last year
- Convolutional Neural Network Implemented in Verilog for System on Chip☆27Updated 6 years ago
- This project aims to develop a novel neuromorphic NoC architecture based on RISC-V ISA to support spiking neural network applications, an…☆21Updated last year
- tpu-systolic-array-weight-stationary☆24Updated 4 years ago
- Hardware accelerator for convolutional neural networks☆50Updated 3 years ago
- CNN-Accelerator based on FPGA developed by verilog HDL.☆48Updated 5 years ago
- A SystemVerilog implementation of Row-Stationary dataflow and Hierarchical Mesh Network-on-Chip Architecture based on Eyeriss CNN Acceler…☆164Updated 5 years ago
- This repository contains full code of Softmax Layer in Verilog☆18Updated 5 years ago
- 16-bit Adder Multiplier hardware on Digilent Basys 3☆77Updated 2 years ago