jerry-D / HedgeHog-Fused-Spiking-Neural-Network-Emulator-Compute-Engine
HedgeHog Fused Spiking Neural Network Emulator/Compute Engine is a hardware implementation of a SNN designed for implementation in Xilinx Kintex Ultra Plus brand FPGAs and embedded RISC-V as trainer.
☆56Updated last year
Alternatives and similar repositories for HedgeHog-Fused-Spiking-Neural-Network-Emulator-Compute-Engine:
Users that are interested in HedgeHog-Fused-Spiking-Neural-Network-Emulator-Compute-Engine are comparing it to the libraries listed below
- A repository FPGA-friendly SNN models☆32Updated 3 years ago
- Spiking Neural Network RTL Implementation☆49Updated 3 years ago
- Hardware implementation of Spiking Neural Network on a PYNQ-Z1 board☆32Updated 5 years ago
- The CyNAPSE Neuromorphic Accelerator: A Digital Spiking neural network accelerator written in fully synthesizable verilog HDL☆32Updated 5 years ago
- CORDIC-SNN, followed with "Unsupervised learning of digital recognition using STDP" published in 2015, frontiers☆21Updated 4 years ago
- tinyODIN digital spiking neural network (SNN) processor - HDL source code and documentation.☆48Updated last year
- A Spiking Neuron Network Project in Verilog Implementation☆20Updated 6 years ago
- FPGA acceleration of a Spike-Timing-Dependent Plasticity learning algorithm for Spiking Neural Networks☆34Updated 4 years ago
- ☆87Updated 4 years ago
- ☆14Updated 3 years ago
- [FPL 2021] SyncNN: Evaluating and Accelerating Spiking Neural Networks on FPGAs.☆53Updated 3 years ago
- ODIN online-learning digital spiking neural network (SNN) processor - HDL source code and documentation.☆171Updated 5 years ago
- FPGA Design of a Spiking Neural Network.☆34Updated 8 months ago
- A project dedicated to developing a hardware Integrated Circuit (IC) for a Spike Neural Network (SNN), powered by the RTL code generated …☆41Updated 11 months ago
- Convolutional Neural Network Implemented in Verilog for System on Chip☆25Updated 5 years ago
- This is the RTL implementation of Shenjing, a low power neuromorphic computing accelerator☆16Updated 4 years ago
- ☆17Updated 3 years ago
- SystemVerilog files for lab project on a DNN hardware accelerator☆13Updated 3 years ago
- IEEE Transactions on Circuits and Systems I: Efficient FPGA Implementations of Pair and Triplet-based STDP for Neuromorphic Architectures☆24Updated 5 years ago
- A three-layer LIF neuron SNN accelerator. The first layer is the input layer and has 784 neurons, that receive the encoded spikes. The se…☆10Updated last year
- ReckOn: A Spiking RNN Processor Enabling On-Chip Learning over Second-Long Timescales - HDL source code and documentation.☆78Updated 2 years ago
- Spiking neural network for Zynq devices with Vivado HLS☆30Updated 6 years ago
- ☆24Updated 2 years ago
- verilog实现TPU中的脉动阵列计算卷积的module☆72Updated 3 years ago
- This project aims to develop a novel neuromorphic NoC architecture based on RISC-V ISA to support spiking neural network applications, an …☆19Updated last year
- Leaky Integrate and Fire (LIF) model implementation for FPGA☆49Updated last year
- A SystemVerilog implementation of Row-Stationary dataflow and Hierarchical Mesh Network-on-Chip Architecture based on Eyeriss CNN Acceler…☆135Updated 5 years ago
- A final semester based group project for EE4218: Embedded Hardware System Design module in NUS where I worked with my teammate to perform…☆12Updated last year
- Spiking neural network implementation using Verilog with LIF (Leaky Integrate-and-Fire) neurons☆14Updated 4 years ago