jerry-D / HedgeHog-Fused-Spiking-Neural-Network-Emulator-Compute-EngineView external linksLinks
HedgeHog Fused Spiking Neural Network Emulator/Compute Engine is a hardware implementation of a SNN designed for implementation in Xilinx Kintex Ultra Plus brand FPGAs and embedded RISC-V as trainer.
☆60Updated this week
Alternatives and similar repositories for HedgeHog-Fused-Spiking-Neural-Network-Emulator-Compute-Engine
Users that are interested in HedgeHog-Fused-Spiking-Neural-Network-Emulator-Compute-Engine are comparing it to the libraries listed below
Sorting:
- SNN on FPGA☆12Apr 26, 2022Updated 3 years ago
- CORDIC-SNN, followed with "Unsupervised learning of digital recognition using STDP" published in 2015, frontiers☆25Feb 9, 2020Updated 6 years ago
- ☆20Apr 7, 2021Updated 4 years ago
- ODIN online-learning digital spiking neural network (SNN) processor - HDL source code and documentation.☆219Apr 20, 2019Updated 6 years ago
- FPGA acceleration of a Spike-Timing-Dependent Plasticity learning algorithm for Spiking Neural Networks☆40Jun 29, 2020Updated 5 years ago
- Spiking Neural Network RTL Implementation☆64Jun 8, 2021Updated 4 years ago
- A repository FPGA-friendly SNN models☆35Mar 24, 2021Updated 4 years ago
- A nest brain simulator based on FPGA(LIF NEURON)☆15Dec 14, 2021Updated 4 years ago
- A three-layer LIF neuron SNN accelerator. The first layer is the input layer and has 784 neurons, that receive the encoded spikes. The se…☆15Sep 9, 2023Updated 2 years ago
- Hardware implementation of Spiking Neural Network on a PYNQ-Z1 board☆39Jun 14, 2019Updated 6 years ago
- This project aims to develop a novel neuromorphic NoC architecture based on RISC-V ISA to support spiking neural network applications, an…☆22Nov 27, 2025Updated 2 months ago
- The CyNAPSE Neuromorphic Accelerator: A Digital Spiking neural network accelerator written in fully synthesizable verilog HDL☆36Sep 25, 2019Updated 6 years ago
- ☆30Jun 8, 2022Updated 3 years ago
- Energy-efficient Event-driven Spiking Neural Network accelerator for FPGA with PyTorch integration☆108Updated this week
- Code for the ISCAS23 paper "The Hardware Impact of Quantization and Pruning for Weights in Spiking Neural Networks"☆11Apr 20, 2023Updated 2 years ago
- FPGA Design of a Spiking Neural Network.☆46May 15, 2024Updated last year
- Spiking neural network for Zynq devices with Vivado HLS☆38Feb 21, 2018Updated 7 years ago
- A Spiking Neuron Network Project in Verilog Implementation☆26Apr 5, 2018Updated 7 years ago
- IEEE Transactions on Circuits and Systems I: Efficient FPGA Implementations of Pair and Triplet-based STDP for Neuromorphic Architectures☆29Jul 7, 2019Updated 6 years ago
- Spiking neural network implementation using Verilog with LIF (Leaky Integrate-and-Fire) neurons☆20Jun 17, 2020Updated 5 years ago
- RISC-V Rocket Chip Strap-on-Booster with Fused Universal Neural Network (FuNN) eNNgine☆21Mar 17, 2022Updated 3 years ago
- Repository collecting papers about neuromorphic hardware, such as ASIC and FPGA implementations of SNNs and stuff.☆205Nov 4, 2023Updated 2 years ago
- [FPL 2021] SyncNN: Evaluating and Accelerating Spiking Neural Networks on FPGAs.☆64Jul 28, 2021Updated 4 years ago
- An FPGA design for simulating biological neurons☆17Jul 5, 2024Updated last year
- tinyODIN digital spiking neural network (SNN) processor - HDL source code and documentation.☆75Mar 30, 2023Updated 2 years ago
- Here is the official code for ICASSP 2024 "Optimal ANN-SNN Conversion with Group Neurons".☆14Mar 1, 2024Updated last year
- ☆20Nov 23, 2022Updated 3 years ago
- ☆100Mar 18, 2020Updated 5 years ago
- ☆16Apr 6, 2022Updated 3 years ago
- Hardware and software implementation of Sparsely-active SNNs☆22Updated this week
- ☆15Sep 27, 2022Updated 3 years ago
- IPs for data-plane integration of Hardware Processing Engines (HWPEs) within a PULP system☆21Jan 17, 2026Updated 3 weeks ago
- This is the RTL implementation of Shenjing, a low power neuromorphic computing accelerator☆17Apr 12, 2020Updated 5 years ago
- ☆31Aug 8, 2020Updated 5 years ago
- This is a fully parameterized verilog implementation of computation kernels for accleration of the Inference of Convolutional Neural Netw…☆194Mar 20, 2024Updated last year
- An energy simulation framework for BPTT-based SNN inference and training.☆17Sep 6, 2023Updated 2 years ago
- A project dedicated to developing a hardware Integrated Circuit (IC) for a Spike Neural Network (SNN), powered by the RTL code generated …☆66Feb 18, 2024Updated last year
- ☆17Mar 2, 2021Updated 4 years ago
- to illustrate how to removal a Neural Network from pc to FPGA board ,it contain all the code include c code worked in pc,HLS prj acceler…☆87May 30, 2021Updated 4 years ago