jerry-D / HedgeHog-Fused-Spiking-Neural-Network-Emulator-Compute-EngineLinks
HedgeHog Fused Spiking Neural Network Emulator/Compute Engine is a hardware implementation of a SNN designed for implementation in Xilinx Kintex Ultra Plus brand FPGAs and embedded RISC-V as trainer.
☆60Updated 7 months ago
Alternatives and similar repositories for HedgeHog-Fused-Spiking-Neural-Network-Emulator-Compute-Engine
Users that are interested in HedgeHog-Fused-Spiking-Neural-Network-Emulator-Compute-Engine are comparing it to the libraries listed below
Sorting:
- Spiking Neural Network RTL Implementation☆60Updated 4 years ago
- A repository FPGA-friendly SNN models☆33Updated 4 years ago
- The CyNAPSE Neuromorphic Accelerator: A Digital Spiking neural network accelerator written in fully synthesizable verilog HDL☆35Updated 6 years ago
- Hardware implementation of Spiking Neural Network on a PYNQ-Z1 board☆38Updated 6 years ago
- SNN on FPGA☆11Updated 3 years ago
- ODIN online-learning digital spiking neural network (SNN) processor - HDL source code and documentation.☆193Updated 6 years ago
- A Spiking Neuron Network Project in Verilog Implementation☆25Updated 7 years ago
- tinyODIN digital spiking neural network (SNN) processor - HDL source code and documentation.☆66Updated 2 years ago
- ☆94Updated 5 years ago
- CORDIC-SNN, followed with "Unsupervised learning of digital recognition using STDP" published in 2015, frontiers☆25Updated 5 years ago
- ☆19Updated 4 years ago
- [FPL 2021] SyncNN: Evaluating and Accelerating Spiking Neural Networks on FPGAs.☆61Updated 4 years ago
- This is the RTL implementation of Shenjing, a low power neuromorphic computing accelerator☆17Updated 5 years ago
- FPGA acceleration of a Spike-Timing-Dependent Plasticity learning algorithm for Spiking Neural Networks☆39Updated 5 years ago
- ☆17Updated 4 years ago
- A three-layer LIF neuron SNN accelerator. The first layer is the input layer and has 784 neurons, that receive the encoded spikes. The se…☆14Updated 2 years ago
- FPGA Design of a Spiking Neural Network.☆43Updated last year
- Spiking neural network implementation using Verilog with LIF (Leaky Integrate-and-Fire) neurons☆19Updated 5 years ago
- Convolutional Neural Network Implemented in Verilog for System on Chip☆27Updated 6 years ago
- Spiking neural network for Zynq devices with Vivado HLS☆35Updated 7 years ago
- ☆27Updated 3 years ago
- CNN-Accelerator based on FPGA developed by verilog HDL.☆48Updated 5 years ago
- The project includes SRAM In Memory Computing Accelerator with updates in design/circuits submitted previously in MPW7, by IITD researche…☆14Updated 2 years ago
- SystemVerilog files for lab project on a DNN hardware accelerator☆17Updated 4 years ago
- This project aims to develop a novel neuromorphic NoC architecture based on RISC-V ISA to support spiking neural network applications, an…☆21Updated last year
- Systolic array based simple TPU for CNN on PYNQ-Z2☆36Updated 3 years ago
- IEEE Transactions on Circuits and Systems I: Efficient FPGA Implementations of Pair and Triplet-based STDP for Neuromorphic Architectures☆26Updated 6 years ago
- Spiking Neural Network Accelerator☆15Updated 3 years ago
- Efficient FPGA-Based Accelerator for Convolutional Neural Networks☆28Updated last year
- Hardware accelerator for convolutional neural networks☆57Updated 3 years ago