jerry-D / HedgeHog-Fused-Spiking-Neural-Network-Emulator-Compute-Engine
HedgeHog Fused Spiking Neural Network Emulator/Compute Engine is a hardware implementation of a SNN designed for implementation in Xilinx Kintex Ultra Plus brand FPGAs and embedded RISC-V as trainer.
☆53Updated last year
Related projects ⓘ
Alternatives and complementary repositories for HedgeHog-Fused-Spiking-Neural-Network-Emulator-Compute-Engine
- A repository FPGA-friendly SNN models☆28Updated 3 years ago
- Spiking Neural Network RTL Implementation☆44Updated 3 years ago
- The CyNAPSE Neuromorphic Accelerator: A Digital Spiking neural network accelerator written in fully synthesizable verilog HDL☆30Updated 5 years ago
- Hardware implementation of Spiking Neural Network on a PYNQ-Z1 board☆28Updated 5 years ago
- tinyODIN digital spiking neural network (SNN) processor - HDL source code and documentation.☆38Updated last year
- FPGA acceleration of a Spike-Timing-Dependent Plasticity learning algorithm for Spiking Neural Networks☆34Updated 4 years ago
- ☆13Updated 3 years ago
- A Spiking Neuron Network Project in Verilog Implementation☆16Updated 6 years ago
- ☆84Updated 4 years ago
- ODIN online-learning digital spiking neural network (SNN) processor - HDL source code and documentation.☆161Updated 5 years ago
- Convolutional Neural Network Implemented in Verilog for System on Chip☆22Updated 5 years ago
- Spiking neural network for Zynq devices with Vivado HLS☆30Updated 6 years ago
- FPGA Design of a Spiking Neural Network.☆32Updated 5 months ago
- This is the RTL implementation of Shenjing, a low power neuromorphic computing accelerator☆16Updated 4 years ago
- [FPL 2021] SyncNN: Evaluating and Accelerating Spiking Neural Networks on FPGAs.☆52Updated 3 years ago
- ☆16Updated 3 years ago
- This project aims to develop a novel neuromorphic NoC architecture based on RISC-V ISA to support spiking neural network applications, an…☆14Updated 11 months ago
- IEEE Transactions on Circuits and Systems I: Efficient FPGA Implementations of Pair and Triplet-based STDP for Neuromorphic Architectures☆22Updated 5 years ago
- A project dedicated to developing a hardware Integrated Circuit (IC) for a Spike Neural Network (SNN), powered by the RTL code generated …☆35Updated 8 months ago
- ☆23Updated 2 years ago
- A SystemVerilog implementation of Row-Stationary dataflow and Hierarchical Mesh Network-on-Chip Architecture based on Eyeriss CNN Acceler…☆128Updated 4 years ago
- CNN-Accelerator based on FPGA developed by verilog HDL.☆45Updated 4 years ago
- ☆11Updated 9 months ago
- SystemVerilog files for lab project on a DNN hardware accelerator☆12Updated 3 years ago
- A three-layer LIF neuron SNN accelerator. The first layer is the input layer and has 784 neurons, that receive the encoded spikes. The se…☆9Updated last year
- tpu-systolic-array-weight-stationary☆18Updated 3 years ago
- 3×3脉动阵列乘法器☆34Updated 5 years ago
- A Flexible and Energy Efficient Accelerator For Sparse Convolution Neural Network☆28Updated 2 months ago
- ReckOn: A Spiking RNN Processor Enabling On-Chip Learning over Second-Long Timescales - HDL source code and documentation.☆75Updated 2 years ago
- verilog实现TPU中的脉动阵列计算卷积的module☆68Updated 2 years ago