A RocketChip rv64imac blinky for yosys/nextpnr/trellis & the Lattice ECP5 fpga
☆26Aug 23, 2019Updated 6 years ago
Alternatives and similar repositories for yoloRISC
Users that are interested in yoloRISC are comparing it to the libraries listed below
Sorting:
- iCE40 floorplan viewer☆24Jun 23, 2018Updated 7 years ago
- ice40 UltraPlus demos☆23Oct 12, 2020Updated 5 years ago
- Python module containing verilog files for rocket cpu (for use with LiteX).☆14Jan 16, 2026Updated last month
- RISC-V Rocket Chip Strap-on-Booster with Fused Universal Neural Network (FuNN) eNNgine☆21Mar 17, 2022Updated 3 years ago
- This repository contains iCEBreaker examples for Amaranth HDL.☆39Oct 31, 2023Updated 2 years ago
- Cross compile FPGA tools☆21Jan 4, 2021Updated 5 years ago
- HiLoTOF -- Hardware-in-the-Loop Test framework for Open FPGAs☆13Feb 9, 2019Updated 7 years ago
- Wavious Wlink☆12Oct 28, 2021Updated 4 years ago
- RISC-V 32-bit core for MCCI Catena 4710☆10Jul 31, 2019Updated 6 years ago
- FPGA Portable Music Generator☆11Aug 1, 2018Updated 7 years ago
- Standard HyperRAM core for ECP5 written in Litex/Migen☆14Dec 6, 2019Updated 6 years ago
- Picorv32 SoC that uses only BRAM, not flash memory☆13Nov 27, 2018Updated 7 years ago
- Verilog Examples and WebFPGA Standard Library☆11Nov 25, 2019Updated 6 years ago
- A Rust embedded HAL crate for LiteX cores☆31Jan 3, 2026Updated last month
- Fluid Pipelines☆11May 4, 2018Updated 7 years ago
- This is an OOT module for GNU Radio integrating verilog simulation feature☆38Sep 23, 2019Updated 6 years ago
- Common SystemVerilog RTL modules for RgGen☆16Feb 5, 2026Updated 3 weeks ago
- There are many RISC V projects on iCE40. This one is mine.☆14Jun 25, 2020Updated 5 years ago
- HDL tools layer for OpenEmbedded☆17Oct 20, 2024Updated last year
- An alternative PnR system, or at least an attempt to get it running on Ubuntu 18.04.☆10Aug 31, 2018Updated 7 years ago
- ice40 UltraPlus demos☆16Oct 4, 2019Updated 6 years ago
- Icarus SIMBUS☆20Nov 6, 2019Updated 6 years ago
- MicroPython - legacy branch contain old experiments, and experimental for new work☆33Sep 6, 2021Updated 4 years ago
- Mirror of https://codeberg.org/ECP5-PCIe/ECP5-PCIe☆102May 16, 2023Updated 2 years ago
- Simplified environment for litex☆14Oct 5, 2020Updated 5 years ago
- ☆15Oct 24, 2019Updated 6 years ago
- Dual MikroBUS board for Upduino 2 FPGA☆18May 24, 2018Updated 7 years ago
- The binaries for SaxonSoc Linux and other configurations☆17Mar 23, 2023Updated 2 years ago
- FPGA config visualized. demo:☆20Mar 17, 2020Updated 5 years ago
- FPGA-based DRAM tester supporting RDIMM DDR5 memories☆28Jan 29, 2026Updated last month
- Combined ESP32C3 and iCE40 FPGA board☆18Jul 13, 2022Updated 3 years ago
- Formal semantics of BSV (Bluespec SystemVerilog), given as a Haskell Program and accompanying document☆18Jul 17, 2016Updated 9 years ago
- OpenDesign Flow Database☆17Oct 31, 2018Updated 7 years ago
- Library of generic verilog buildingblocks☆17Dec 25, 2025Updated 2 months ago
- Experimental Lattice ECP5-driven Data Center Security Communication Module☆20Jul 22, 2024Updated last year
- Industry standard I/O for nMigen☆12Apr 23, 2020Updated 5 years ago
- Tool to parse yosys and nextpnr logfiles to then plot LUT, flip-flop and maximum frequency stats as your project progresses.☆22Oct 24, 2023Updated 2 years ago
- RISCV Gem5 simulator flow for Architetture dei Sistemi di Elaborazione☆31Nov 5, 2025Updated 3 months ago
- Adapter to use Colorlight i5/i9 FPGA boards in a QMTech board form factor☆20Jul 23, 2022Updated 3 years ago