Alternatives and similar repositories for FPGA_AI_Edge_Contest_2019

Users that are interested in FPGA_AI_Edge_Contest_2019 are comparing it to the libraries listed below

• fpga-design-contest / ad-refkit
  autonomous driving contest reference kit
  ☆10Updated 3 years ago
• HirokiNakahara / FPGA_lecture
  Source Codes for a lecture entitled "Parallel and Reconfigurable VLSI Computing" in Tokyo Tech.
  ☆28Updated 4 years ago
• lp6m / ImageDetectionHW2
  HOG + SVM on FPGA
  ☆26Updated 4 years ago
• fixstars / xg_mac
  10G Ethernet MAC implementation
  ☆21Updated 4 years ago
• gewuek / vitis_ai_custom_platform_flow
  This project is trying to create a base vitis platform to run with DPU
  ☆47Updated 4 years ago
• Xilinx / logicnets
  ☆94Updated 11 months ago
• Hosseinabady / SDSoC-Benchmarks
  ☆16Updated 4 years ago
• jgoeders / dac_sdc_2020_designs
  Designs for finalist teams of the DAC System Design Contest
  ☆37Updated 4 years ago
• ryuz / jelly
  Original FPGA platform
  ☆65Updated this week
• jgoeders / dac_sdc_2021
  ☆23Updated 3 years ago
• Avnet / vitis
  Vitis Repository for Avnet Designs
  ☆9Updated 2 months ago
• cathalmccabe / pynq-z1_board_files
  PYNQ-Z1 board files for Vivado
  ☆34Updated 3 years ago
• tukl-msd / LSTM-PYNQ
  ☆29Updated 7 years ago
• fixstars / ultra96_design
  Repository of HW design and SW for Ultra96 board + MIPI board
  ☆17Updated 6 years ago
• lp6m / VexRiscv_Ultra96
  Implementation VexRiscv on ultra96
  ☆12Updated 3 years ago
• ikwzm / ZynqMP-FPGA-Linux
  FPGA+SoC+Linux+Device Tree Overlay+FPGA Manager U-Boot&Linux Kernel&Debian11 Images (for Xilinx:Zynq Ultrascale+ MPSoC)
  ☆129Updated last year
• KastnerRG / Spector-HLS
  Contains FPGA benchmarks for Vivado HLS and Catapult HLS
  ☆26Updated 4 years ago
• template-hls / template-hls-float
  ☆29Updated 6 years ago
• ikwzm / ZynqMP-FPGA-Ubuntu18.04-Ultra96
  Ubuntu 18.04 Desktop for Ultra96/Ultra96-V2
  ☆19Updated 5 years ago
• jgoeders / dac_sdc_2020
  DAC System Design Contest 2020
  ☆29Updated 4 years ago
• Licheng-Guo / vivado-hls-broadcast-optimization
  [DAC 2020] Analysis and Optimization of the Implicit Broadcasts in FPGA HLS to Improve Maximum Frequency
  ☆32Updated 4 years ago
• ryuz / BinaryBrain
  Binary Neural Network Framework for FPGA(Differentiable LUT)
  ☆158Updated 6 months ago
• DreamIP / haddoc2
  Caffe to VHDL
  ☆67Updated 4 years ago
• drichmond / PYNQ-HLS
  A Tutorial on Putting High-Level Synthesis cores in PYNQ
  ☆105Updated 7 years ago
• splineai-cloud / COVID-XS
  CNN based Deep Learning for Detecting COVID-19 from X-Ray images.The Deep Learning is deployed in AWS IoT GreenGrass with Xilinx ZCU104 …
  ☆19Updated 4 years ago
• polyphony-dev / polyphony
  Polyphony is Python based High-Level Synthesis compiler.
  ☆105Updated 4 months ago
• DPCEKY / systolic-array
  HLS implemented systolic array structure
  ☆41Updated 7 years ago
• awai54st / LUTNet
  ☆58Updated 5 years ago
• Xilinx / HLS_arbitrary_Precision_Types
  ☆46Updated last year
• PeterOgden / overlay_tutorial
  Premade bitstreams and block designs to complemented the PYNQ overlay tutorial
  ☆40Updated 3 years ago