Alternatives and similar repositories for FPGA_AI_Edge_Contest_2019

Users that are interested in FPGA_AI_Edge_Contest_2019 are comparing it to the libraries listed below

• DreamIP / haddoc2
  Caffe to VHDL
  ☆67Updated 5 years ago
• Xilinx / pyxir
  ☆37Updated 3 years ago
• Xilinx / logicnets
  Train and deploy LUT-based neural networks on FPGAs
  ☆98Updated last year
• HirokiNakahara / FPGA_lecture
  Source Codes for a lecture entitled "Parallel and Reconfigurable VLSI Computing" in Tokyo Tech.
  ☆28Updated 4 years ago
• EECS-NTNU / bismo
  BISMO: A Scalable Bit-Serial Matrix Multiplication Overlay for Reconfigurable Computing
  ☆141Updated 5 years ago
• isuckatdrifting / Zeus
  NVDLA small config implementation on Zynq ZCU104 (evaluation)
  ☆23Updated 6 years ago
• ryuz / BinaryBrain
  Binary Neural Network Framework for FPGA(Differentiable LUT)
  ☆162Updated 3 weeks ago
• Xilinx / ResNet50-PYNQ
  Quantized ResNet50 Dataflow Acceleration on Alveo, with PYNQ
  ☆59Updated 3 years ago
• jgoeders / dac_sdc_2020_designs
  Designs for finalist teams of the DAC System Design Contest
  ☆37Updated 5 years ago
• template-hls / template-hls-float
  ☆30Updated 6 years ago
• fpga-design-contest / ad-refkit
  autonomous driving contest reference kit
  ☆10Updated 3 years ago
• UCLA-VAST / FlexCNN
  ☆72Updated 2 years ago
• awai54st / LUTNet
  ☆58Updated 5 years ago
• jgoeders / dac_sdc_2021
  ☆23Updated 3 years ago
• gewuek / vitis_ai_custom_platform_flow
  This project is trying to create a base vitis platform to run with DPU
  ☆48Updated 5 years ago
• Xilinx / HLS_arbitrary_Precision_Types
  ☆46Updated last year
• DNN-Accelerators / Open-Source-IPs
  ☆34Updated 6 years ago
• Hosseinabady / SDSoC-Benchmarks
  ☆16Updated 4 years ago
• AlexMontgomerie / fpgaconvnet-model
  Performance and resource models for fpgaConvNet: a Streaming-Architecture-based CNN Accelerator.
  ☆30Updated 9 months ago
• os-hxfan / Static_BFP_CNN
  Static Block Floating Point Quantization for CNN
  ☆34Updated 4 years ago
• lp6m / ImageDetectionHW2
  HOG + SVM on FPGA
  ☆27Updated 4 years ago
• DPCEKY / systolic-array
  HLS implemented systolic array structure
  ☆41Updated 7 years ago
• Avnet / Ultra96-PYNQ
  Board files to build Ultra 96 PYNQ image
  ☆157Updated 8 months ago
• AlexMontgomerie / samo
  SAMO: Streaming Architecture Mapping Optimisation
  ☆34Updated last year
• drichmond / PYNQ-HLS
  A Tutorial on Putting High-Level Synthesis cores in PYNQ
  ☆107Updated 7 years ago
• Licheng-Guo / vivado-hls-broadcast-optimization
  [DAC 2020] Analysis and Optimization of the Implicit Broadcasts in FPGA HLS to Improve Maximum Frequency
  ☆32Updated 4 years ago
• Xilinx / gemx
  Matrix Operation Library for FPGA https://xilinx.github.io/gemx/
  ☆63Updated 5 years ago
• fpgasystems / ZipML-PYNQ
  Linear model training using stochastic gradient descent (SGD) on PYNQ with full to low precision.
  ☆55Updated 7 years ago
• HirokiNakahara / GUINNESS
  GUINNESS: A GUI-based binarized deep Neural NEtwork SyntheSizer toward an FPGA
  ☆181Updated 6 years ago
• jgoeders / dac_sdc_2021_designs
  ☆20Updated 3 years ago