☆19Aug 10, 2020Updated 5 years ago
Alternatives and similar repositories for PVS464
Users that are interested in PVS464 are comparing it to the libraries listed below. We may earn a commission when you buy through links labeled 'Ad' on this page.
Sorting:
- As a salute to the guy who inspired me to become EE engineer. This is the RTL version of his homebrew CPU core (KC-LS1u)☆17Oct 23, 2025Updated 8 months ago
- ☆18Dec 21, 2020Updated 5 years ago
- RISC-V Rocket Chip Strap-on-Booster with Fused Universal Neural Network (FuNN) eNNgine☆21Mar 17, 2022Updated 4 years ago
- ASIC Design of the openSPARC Floating Point Unit☆17Mar 13, 2017Updated 9 years ago
- digital recognition base on FPGA☆12Nov 10, 2019Updated 6 years ago
- Deploy on Railway without the complexity - Free Credits Offer • AdConnect your repo and Railway handles the rest with instant previews. Quickly provision container image services, databases, and storage volumes.
- My project for the course "Logic and Computer Design Fundamentals"(LCDF) in Zhejiang University☆12May 14, 2017Updated 9 years ago
- A Reconfigurable Accelerator for Deep Convolutional Neural Networks Implemented by Chisel3.☆29Jul 14, 2021Updated 4 years ago
- [DATE'2025, TCAD'2025] Terafly : A Multi-Node FPGA Based Accelerator Design for Efficient Cooperative Inference in LLMs☆37Nov 13, 2025Updated 7 months ago
- Example Codes for Snorkeling in Verilog Bay☆17Sep 9, 2016Updated 9 years ago
- ahb scram controller, design and verification☆29Jun 20, 2018Updated 8 years ago
- Flappy Bird on Verilog☆16Jun 6, 2023Updated 3 years ago
- ☆19Jul 21, 2020Updated 5 years ago
- A small 32-bit implementation of the RISC-V architecture☆33Apr 10, 2026Updated 2 months ago
- 一种基于FPGA平台的实时视频去雾系统项目代码，其中bit流文件可以直接下载到PYNQ-Z2开发板上，通过usb和hdmi设备输入有雾视频，将去雾后的视频输出到显示屏上。c++源代码部分是我们的去雾IP核的源代码。☆20Nov 24, 2019Updated 6 years ago
- Virtual machines for every use case on DigitalOcean • AdGet dependable uptime with 99.99% SLA, simple security tools, and predictable monthly pricing with DigitalOcean's virtual machines, called Droplets.
- Using VexRiscv without installing Scala☆39Nov 10, 2021Updated 4 years ago
- Raptor is an SoC Design Template based on Arm Cortex M0 or M3 core.☆22Oct 9, 2019Updated 6 years ago
- Devotes to open source FPGA☆28May 9, 2020Updated 6 years ago
- ☆14Oct 19, 2018Updated 7 years ago
- ☆31Aug 8, 2020Updated 5 years ago
- Binary Single Precision Floating-point Fused Multiply-Add Unit Design (Verilog HDL)☆22Jul 8, 2013Updated 12 years ago
- ☆11Jul 4, 2023Updated 3 years ago
- openMSP430 CPU core (from OpenCores)☆22Oct 14, 2022Updated 3 years ago
- ☆28Nov 15, 2019Updated 6 years ago
- Managed Kubernetes at scale on DigitalOcean • AdDigitalOcean Kubernetes includes the control plane, bandwidth allowance, container registry, automatic updates, and more for free.
- ☆11Jul 16, 2020Updated 5 years ago
- ☆23Dec 7, 2019Updated 6 years ago
- ☆11Dec 4, 2023Updated 2 years ago
- ☆14Jul 17, 2020Updated 5 years ago
- Pan's 1st Gen RISC-V SoC, contains a 12T multicycle RISC-V32ia core, with an EMIF-like simple bus☆16Oct 21, 2020Updated 5 years ago
- KitProg3 Firmware repo☆17Mar 31, 2026Updated 3 months ago
- SEGA Genesis/Megadrive core, running on a Altera/Terasic DE1 board.☆10Jul 15, 2021Updated 4 years ago
- Implementation of SHA256 Hasher with UART Transceiver in Verilog. Designed to run on Altera's DE2 FPGA Development Board.☆16Oct 16, 2018Updated 7 years ago
- Systolic matrix multiplication kernel implemented on Xilinx PYNQ FPGA board☆16Jun 23, 2020Updated 6 years ago
- 1-Click AI Models by DigitalOcean Gradient • AdDeploy popular AI models on DigitalOcean Gradient GPU virtual machines with just a single click. Zero configuration with optimized deployments.
- ☆20Nov 3, 2016Updated 9 years ago
- ☆18Jul 28, 2022Updated 3 years ago
- This repository is outdated and the related functionality has been migrated to https://github.com/easysoc/easysoc-firrtl☆11Nov 3, 2021Updated 4 years ago
- 10_100_1000 Mbps tri-mode ethernet MAC☆11Jul 17, 2014Updated 11 years ago
- An experimental System-on-Chip with a custom compiler toolchain.☆59Jan 2, 2020Updated 6 years ago
- Pipelined DCPU-16 Verilog Implementation☆42May 30, 2012Updated 14 years ago
- OpenFPGA ICE40UP5K☆36Aug 8, 2020Updated 5 years ago