Alternatives and similar repositories for uvm-components

Users that are interested in uvm-components are comparing it to the libraries listed below

• pulp-platform / axi2apb
  ☆21Updated 5 years ago
• isuckatdrifting / Gaia
  Generate UVM testbench framework template files with Python 3
  ☆26Updated 5 years ago
• PacoReinaCampo / MPSoC-DV
  Multi-Processor System on Chip verified with UVM/OSVVM/FV
  ☆35Updated 6 months ago
• zhajio1988 / ExtremeDV_UVM
  UVM resource from github, run simulation use YASAsim flow
  ☆31Updated 5 years ago
• pulp-platform / common_verification
  SystemVerilog modules and classes commonly used for verification
  ☆51Updated last week
• chad-q / andes-vector-riscv-dv
  Andes Vector Extension support added to riscv-dv
  ☆17Updated 5 years ago
• pulp-platform / axi_spi_master
  ☆22Updated 6 years ago
• pulp-platform / apb
  APB Logic
  ☆22Updated 3 weeks ago
• adki / DPI_Tutorial
  SystemVerilog Direct Programming Interface (DPI) Tutorial
  ☆72Updated 4 years ago
• jerralph / riscv-vip
  For pre-silicon developers of RISC-V systems, riscv-vip is a SystemVerilog project that helps with pre-si verification and debug
  ☆65Updated 4 years ago
• openhwgroup / core-v-mcu-uvm
  CORE-V MCU UVM Environment and Test Bench
  ☆24Updated last year
• pulp-platform / axi_llc
  ☆32Updated last week
• zebmehring / Processor-Cache
  A Verilog implementation of a processor cache.
  ☆34Updated 7 years ago
• aignacio / axi_dma
  General Purpose AXI Direct Memory Access
  ☆61Updated last year
• RoaLogic / ahb3lite_apb_bridge
  Parameterised Asynchronous AHB3-Lite to APB4 Bridge.
  ☆47Updated last year
• chiggs / UVM
  Mirror of the Universal Verification Methodology from sourceforge
  ☆35Updated 10 years ago
• loghall / axi_cache
  verification of simple axi-based cache
  ☆18Updated 6 years ago
• StanfordAHA / AhaM3SoC
  SoC Based on ARM Cortex-M3
  ☆34Updated 6 months ago
• muzafferkal / axi-bfm
  AXI3 Bus Functional Models (Initiator & Target)
  ☆29Updated 2 years ago
• doswellf / combinator-uvm
  UVM Testbench For SystemVerilog Combinator Implementation
  ☆56Updated 8 years ago
• RoaLogic / plic
  Platform Level Interrupt Controller
  ☆44Updated last year
• PacoReinaCampo / SoC-DV
  System on Chip verified with UVM/OSVVM/FV
  ☆32Updated 6 months ago
• kumarrishav14 / AMBA_APB
  To design test bench of the APB protocol
  ☆18Updated 4 years ago
• riscv-verification / riscvISACOV
  SystemVerilog Functional Coverage for RISC-V ISA
  ☆32Updated 6 months ago
• jiacaiyuan / uvm-generator
  UVM Auto Generate ; Verify Project Build; Verilog Instance
  ☆35Updated 5 years ago
• EngAhmed21 / RISC-V-Processor-with-Pipelining
  Implementation of the pipelined RISC V processor with many useful features as fully bypassing, dynamic branch prediction, single and mult…
  ☆17Updated last year
• tej-chavan / Design-and-Verification-of-DDR3-Memory-Controller
  The memory model was leveraged from micron.
  ☆24Updated 7 years ago
• mbits-mirafra / axi4_avip
  ☆37Updated 6 months ago
• iammituraj / skid_buffer
  Skid Buffer and Pipeline Skid Buffer designed in Verilog/System Verilog.
  ☆26Updated last month
• funannoka / SoC-Design-DDR3-Controller
  DDR3 SDRAM Memory Controller Design & Synthesis using System Verilog
  ☆31Updated 7 years ago