anycore / anycore-riscv-src
The RTL source for AnyCore RISC-V
☆30Updated 2 years ago
Alternatives and similar repositories for anycore-riscv-src:
Users that are interested in anycore-riscv-src are comparing it to the libraries listed below
- ☆32Updated last week
- DUTH RISC-V Superscalar Microprocessor☆29Updated 3 months ago
- Advanced Architecture Labs with CVA6☆54Updated last year
- Tests for example Rocket Custom Coprocessors☆69Updated 4 years ago
- ☆23Updated last month
- Transactional Verilog design and Verilator Testbench for a RISC-V TensorCore Vector co-processor for reproducible linear algebra☆50Updated 3 years ago
- Simple UVM environment for experimenting with Verilator.☆16Updated last month
- A 32-bit RISC-V Processor Designed with High-Level Synthesis☆52Updated 5 years ago
- A RISC-V 32 bits, Out Of Order, single issue with branch prediction CPU, implementing the B, C, M and Zfinx extensions.☆16Updated last month
- ☆27Updated 2 months ago
- CHIPKIT: An agile, reusable open-source framework for rapid test chip development☆40Updated 4 years ago
- For contributions of Chisel IP to the chisel community.☆59Updated 3 months ago
- LIS Network-on-Chip Implementation☆29Updated 8 years ago
- Tightly-coupled cache coherence unit for CVA6 using the ACE protocol☆30Updated 9 months ago
- RISCV core RV32I/E.4 threads in a ring architecture☆31Updated last year
- Proposed RISC-V Composable Custom Extensions Specification☆69Updated 9 months ago
- Open source RTL simulation acceleration on commodity hardware☆23Updated last year
- The 3rd Iteration of the Berkeley RISC-V DMA Accelerator☆26Updated 5 years ago
- Setup scripts and files needed to compile CoreMark on RISC-V☆64Updated 6 months ago
- Platform Level Interrupt Controller☆36Updated 9 months ago
- SystemVerilog Functional Coverage for RISC-V ISA☆25Updated 4 months ago
- RiftCore is a 9-stage, single-issue, out-of-order 64-bits RISC-V Core, which supports RV64IMC and 3-level Cache System☆37Updated 2 years ago
- C/Assembly macros for talking with Rocket Custom Coprocessors (RoCCs)☆52Updated 4 years ago
- ☆17Updated 2 years ago
- Chisel Cheatsheet☆32Updated last year
- Original test vector of RISC-V Vector Extension☆11Updated 3 years ago
- A Rocket-based RISC-V superscalar in-order core☆29Updated last week
- RTL sources of the High-Performance L1 Dcache (HPDcache) for OpenHW CV cores☆64Updated 2 weeks ago
- HLS for Networks-on-Chip☆33Updated 3 years ago
- ☆40Updated 5 years ago