ic-lab-duth / DRIM
DUTH RISC-V Microprocessor
☆18Updated 3 years ago
Related projects: ⓘ
- DUTH RISC-V Superscalar Microprocessor☆29Updated 4 months ago
- Andes Vector Extension support added to riscv-dv☆14Updated 4 years ago
- SystemVerilog Functional Coverage for RISC-V ISA☆22Updated 7 months ago
- A barebones 64-bit RISC-V micro-controller class CPU, implementing the I(nteger), M(ul/div), C(ompressed) and K(ryptography) extensions.☆43Updated 2 years ago
- Development of a Network on Chip Simulation using SystemC.☆30Updated 7 years ago
- ☆35Updated 5 years ago
- 128KB AXI cache (32-bit in, 256-bit out)☆39Updated 3 years ago
- ☆19Updated 4 years ago
- The memory model was leveraged from micron.☆18Updated 6 years ago
- General Purpose AXI Direct Memory Access☆44Updated 4 months ago
- Single-Cycle RISC-V Processor in systemverylog☆19Updated 5 years ago
- ☆22Updated 6 months ago
- HW-SW Co-Simulation Library for AMBA AXI BFM using DPI/VPI☆28Updated 3 years ago
- SoC Based on ARM Cortex-M3☆24Updated 4 months ago
- Xilinx AXI VIP example of use☆29Updated 3 years ago
- SystemVerilog Direct Programming Interface (DPI) Tutorial☆43Updated 3 years ago
- CV32E40P is an in-order 4-stage RISC-V RV32IMFCXpulp CPU based on RI5CY from PULP-Platform☆16Updated 5 months ago
- Repository gathering basic modules for CDC purpose☆49Updated 4 years ago
- IPs for data-plane integration of Hardware Processing Engines (HWPEs) within a PULP system☆18Updated last month
- Prototype-network-on-chip (ProNoC) is an EDA tool that facilitates prototyping of custom heterogeneous NoC-based many-core-SoC (MCSoC).☆43Updated 3 months ago
- Implementation of post-process coverage, and batch waveform search☆15Updated 3 years ago
- AXI3 Bus Functional Models (Initiator & Target)☆26Updated last year
- ☆22Updated 7 months ago
- Common SystemVerilog package used by all RoaLogic IP with AMBA AHB3-Lite interfaces☆15Updated 4 months ago
- CORE-V MCU UVM Environment and Test Bench☆16Updated 2 months ago
- Platform Level Interrupt Controller☆34Updated 4 months ago
- APB UVC ported to Verilator☆11Updated 10 months ago
- ☆23Updated 4 years ago
- ☆24Updated 5 years ago
- 100DaysofRTL & System Verilog design: basic logic gates, mux, half/full subtractor, Encoder, D flipflop, 8 bit counter, LFSR, Custom Coun…☆26Updated last year