Alternatives and similar repositories for DRIM

Users that are interested in DRIM are comparing it to the libraries listed below

• ic-lab-duth / DRIM-S
  DUTH RISC-V Superscalar Microprocessor
  ☆31Updated 11 months ago
• pulp-platform / axi_llc
  ☆29Updated 2 weeks ago
• ben-marshall / croyde-riscv
  A barebones 64-bit RISC-V micro-controller class CPU, implementing the I(nteger), M(ul/div), C(ompressed) and K(ryptography) extensions.
  ☆47Updated 3 years ago
• jessebarreto / NetworkOnChip
  Development of a Network on Chip Simulation using SystemC.
  ☆34Updated 8 years ago
• ic-lab-duth / NoCpad
  HLS for Networks-on-Chip
  ☆36Updated 4 years ago
• pulp-platform / axi_spi_master
  ☆21Updated 6 years ago
• pulp-platform / cv32e40p
  CV32E40P is an in-order 4-stage RISC-V RV32IMFCXpulp CPU based on RI5CY from PULP-Platform
  ☆19Updated 2 months ago
• pulp-platform / common_verification
  SystemVerilog modules and classes commonly used for verification
  ☆50Updated 9 months ago
• hyoukjun / microswitch-noc
  ☆27Updated 5 years ago
• esynr3z / axi_vip_demo
  Xilinx AXI VIP example of use
  ☆42Updated 4 years ago
• RoaLogic / plic
  Platform Level Interrupt Controller
  ☆43Updated last year
• aignacio / axi_dma
  General Purpose AXI Direct Memory Access
  ☆59Updated last year
• chipsalliance / aib-protocols
  ☆27Updated last year
• pulp-platform / apb
  APB Logic
  ☆20Updated this week
• pulp-platform / ace
  ☆19Updated last month
• riscv-verification / riscvISACOV
  SystemVerilog Functional Coverage for RISC-V ISA
  ☆30Updated 4 months ago
• varunnagpaal / Digital-Hardware-Modelling
  Digital Hardware Modelling using VHDL, Verilog, SystemVerilog, SystemC, HLS(C++, OpenCL)
  ☆67Updated 7 months ago
• chad-q / andes-vector-riscv-dv
  Andes Vector Extension support added to riscv-dv
  ☆17Updated 5 years ago
• openhwgroup / core-v-mcu-uvm
  CORE-V MCU UVM Environment and Test Bench
  ☆24Updated last year
• iammituraj / skid_buffer
  Skid Buffer and Pipeline Skid Buffer designed in Verilog/System Verilog.
  ☆22Updated last year
• pulp-platform / fpu_div_sqrt_mvp
  [UNRELEASED] FP div/sqrt unit for transprecision
  ☆24Updated last month
• TUM-LIS / lisnoc
  LIS Network-on-Chip Implementation
  ☆31Updated 9 years ago
• ljgibbslf / basic_cache_core
  ☆29Updated 5 years ago
• chipsalliance / uvm-verilator
  ☆98Updated 2 years ago
• StanfordAHA / AhaM3SoC
  SoC Based on ARM Cortex-M3
  ☆33Updated 4 months ago
• Youssefmdany / Design-and-UVM-TB-of-RISC-V-Microprocessor
  Design and UVM-TB of RISC -V Microprocessor
  ☆28Updated last year
• pulp-platform / axi_mem_if
  Simple single-port AXI memory interface
  ☆46Updated last year
• pulp-platform / fpu
  ☆54Updated 6 years ago
• openhwgroup / cv-hpdcache
  RTL sources of the High-Performance L1 Dcache (HPDcache) for OpenHW CV cores
  ☆90Updated last month
• pulp-platform / axi_riscv_atomics
  AXI Adapter(s) for RISC-V Atomic Operations
  ☆66Updated 3 weeks ago