ic-lab-duth / DRIM
DUTH RISC-V Microprocessor
☆19Updated 3 months ago
Alternatives and similar repositories for DRIM:
Users that are interested in DRIM are comparing it to the libraries listed below
- DUTH RISC-V Superscalar Microprocessor☆30Updated 5 months ago
- ☆21Updated 5 years ago
- LEN5 is a configurable, speculative, out-of-order, 64-bit RISC-V microprocessor targetting etherogeneus systems on chip.☆15Updated 10 months ago
- CORE-V MCU UVM Environment and Test Bench☆20Updated 8 months ago
- ☆26Updated 5 years ago
- SystemVerilog overhaul of ESP L2 and LLC caches with directory based protocol☆17Updated last month
- Skid Buffer and Pipeline Skid Buffer designed in Verilog/System Verilog.☆18Updated 7 months ago
- The memory model was leveraged from micron.☆22Updated 7 years ago
- General Purpose AXI Direct Memory Access☆49Updated 10 months ago
- Andes Vector Extension support added to riscv-dv☆14Updated 4 years ago
- Development of a Network on Chip Simulation using SystemC.☆31Updated 7 years ago
- CV32E40P is an in-order 4-stage RISC-V RV32IMFCXpulp CPU based on RI5CY from PULP-Platform☆19Updated last month
- 128KB AXI cache (32-bit in, 256-bit out)☆48Updated 3 years ago
- Binary Single Precision Floating-point Fused Multiply-Add Unit Design (Verilog HDL)☆18Updated 11 years ago
- A barebones 64-bit RISC-V micro-controller class CPU, implementing the I(nteger), M(ul/div), C(ompressed) and K(ryptography) extensions.☆44Updated 3 years ago
- ☆31Updated 5 years ago
- ☆11Updated 3 years ago
- verification of simple axi-based cache☆18Updated 5 years ago
- SoC Based on ARM Cortex-M3☆29Updated 2 weeks ago
- SystemVerilog modules and classes commonly used for verification☆46Updated 2 months ago
- IPs for data-plane integration of Hardware Processing Engines (HWPEs) within a PULP system☆19Updated last month
- Implementation of post-process coverage, and batch waveform search☆15Updated 3 years ago
- Implementation of the pipelined RISC V processor with many useful features as fully bypassing, dynamic branch prediction, single and mult…☆14Updated last year
- SystemVerilog Functional Coverage for RISC-V ISA☆25Updated 6 months ago
- ☆26Updated 4 years ago
- HLS for Networks-on-Chip☆33Updated 4 years ago
- ☆24Updated last month
- Xilinx AXI VIP example of use☆34Updated 3 years ago
- ☆19Updated 5 years ago
- ☆23Updated last year