ic-lab-duth / DRIMLinks
DUTH RISC-V Microprocessor
☆20Updated 7 months ago
Alternatives and similar repositories for DRIM
Users that are interested in DRIM are comparing it to the libraries listed below
Sorting:
- DUTH RISC-V Superscalar Microprocessor☆31Updated 8 months ago
- SystemVerilog Functional Coverage for RISC-V ISA☆29Updated last month
- Andes Vector Extension support added to riscv-dv☆17Updated 5 years ago
- Multi-Processor System on Chip verified with UVM/OSVVM/FV☆32Updated last month
- General Purpose AXI Direct Memory Access☆53Updated last year
- LIS Network-on-Chip Implementation☆30Updated 8 years ago
- Digital Hardware Modelling using VHDL, Verilog, SystemVerilog, SystemC, HLS(C++, OpenCL)☆66Updated 5 months ago
- Platform Level Interrupt Controller☆41Updated last year
- 128KB AXI cache (32-bit in, 256-bit out)☆51Updated 4 years ago
- ☆27Updated 5 years ago
- ☆26Updated last year
- Binary Single Precision Floating-point Fused Multiply-Add Unit Design (Verilog HDL)☆19Updated 12 years ago
- Network on Chip for MPSoC☆26Updated last month
- ☆30Updated this week
- Development of a Network on Chip Simulation using SystemC.☆34Updated 8 years ago
- A barebones 64-bit RISC-V micro-controller class CPU, implementing the I(nteger), M(ul/div), C(ompressed) and K(ryptography) extensions.☆45Updated 3 years ago
- ☆29Updated 4 years ago
- SoC Based on ARM Cortex-M3☆32Updated last month
- ☆16Updated 2 weeks ago
- Proposed RISC-V Composable Custom Extensions Specification☆71Updated 2 weeks ago
- work in SSRL, SOC/NOC/Chiplet Design, DDR/UCIe/PCIe, UVM Framework☆34Updated 2 years ago
- LCAI-TIHU HW is an AI inference processor which is comprised of RISC-V cpu, nvdla, NoC bus, PCIe module, DDR, SRAM, bootROM, DMA and peri…☆41Updated 2 years ago
- IPs for data-plane integration of Hardware Processing Engines (HWPEs) within a PULP system☆19Updated last week
- SAURIA (Systolic-Array tensor Unit for aRtificial Intelligence Acceleration) is an open-source Convolutional Neural Network accelerator b…☆51Updated 9 months ago
- The memory model was leveraged from micron.☆22Updated 7 years ago
- BlackParrot on Zynq☆43Updated 4 months ago
- CORE-V MCU UVM Environment and Test Bench☆21Updated 11 months ago
- HLS for Networks-on-Chip☆35Updated 4 years ago
- Implementation of the pipelined RISC V processor with many useful features as fully bypassing, dynamic branch prediction, single and mult…☆14Updated last year
- SystemVerilog modules and classes commonly used for verification☆50Updated 6 months ago