Alternatives and similar repositories for andes-vector-riscv-dv

Users that are interested in andes-vector-riscv-dv are comparing it to the libraries listed below

• loghall / axi_cache
  verification of simple axi-based cache
  ☆18Updated 6 years ago
• PacoReinaCampo / MPSoC-DV
  Multi-Processor System on Chip verified with UVM/OSVVM/FV
  ☆30Updated last week
• openhwgroup / core-v-mcu-uvm
  CORE-V MCU UVM Environment and Test Bench
  ☆21Updated 10 months ago
• StanfordAHA / AhaM3SoC
  SoC Based on ARM Cortex-M3
  ☆32Updated 2 weeks ago
• riscv-verification / riscvISACOV
  SystemVerilog Functional Coverage for RISC-V ISA
  ☆28Updated 8 months ago
• wanderingnail / AXI_DMA
  ☆20Updated 2 years ago
• pulp-platform / axi2apb
  ☆20Updated 5 years ago
• ShonTaware / LowPower
  Various low power labs using sky130
  ☆12Updated 3 years ago
• LCAI-TIHU / HW
  LCAI-TIHU HW is an AI inference processor which is comprised of RISC-V cpu, nvdla, NoC bus, PCIe module, DDR, SRAM, bootROM, DMA and peri…
  ☆37Updated 2 years ago
• avashist003 / FIFO_SystemVerilog_Assertion
  Synchronous FIFO design & verification using systemVerilog Assertions
  ☆16Updated 3 years ago
• pulp-platform / axi_spi_master
  ☆21Updated 5 years ago
• ultraembedded / core_axi_cache
  128KB AXI cache (32-bit in, 256-bit out)
  ☆49Updated 4 years ago
• yvnr4you / AMBA_AXI3
  System Verilog and Emulation. Written all the five channels.
  ☆34Updated 8 years ago
• jiacaiyuan / uvm-generator
  UVM Auto Generate ; Verify Project Build; Verilog Instance
  ☆34Updated 5 years ago
• taichi-ishitani / tue
  Useful UVM extensions
  ☆22Updated 10 months ago
• ic-lab-duth / DRIM-S
  DUTH RISC-V Superscalar Microprocessor
  ☆31Updated 7 months ago
• funannoka / SoC-Design-DDR3-Controller
  DDR3 SDRAM Memory Controller Design & Synthesis using System Verilog
  ☆31Updated 6 years ago
• pulp-platform / axi_llc
  ☆29Updated last month
• imokanj / clk_rst_agent
  UVM Clock and Reset Agent
  ☆13Updated 7 years ago
• RoaLogic / plic
  Platform Level Interrupt Controller
  ☆40Updated last year
• aignacio / axi_dma
  General Purpose AXI Direct Memory Access
  ☆50Updated last year
• tej-chavan / Design-and-Verification-of-DDR3-Memory-Controller
  The memory model was leveraged from micron.
  ☆22Updated 7 years ago
• JoseIuri / UVM_Python_UVMC
  This repository contains an example of the connection between an UVM Testbench and a Python reference model using UVM Connect from Mentor…
  ☆16Updated 5 years ago
• open-dv / dma_axi
  ☆16Updated 6 years ago
• nguyenquanicd / AllArbiterRTLCode
  RTL code of some arbitration algorithm
  ☆14Updated 5 years ago
• isuckatdrifting / Gaia
  Generate UVM testbench framework template files with Python 3
  ☆26Updated 5 years ago
• pulp-platform / fpu_div_sqrt_mvp
  [UNRELEASED] FP div/sqrt unit for transprecision
  ☆22Updated last year
• taichi-ishitani / tvip-common
  ☆12Updated 11 months ago
• emmanouil-komninos / jtag_vip_uvm
  ☆12Updated 9 years ago
• pulp-platform / axi_mem_if
  Simple single-port AXI memory interface
  ☆41Updated 11 months ago