chad-q / andes-vector-riscv-dvView external linksLinks
Andes Vector Extension support added to riscv-dv
☆18May 29, 2020Updated 5 years ago
Alternatives and similar repositories for andes-vector-riscv-dv
Users that are interested in andes-vector-riscv-dv are comparing it to the libraries listed below
Sorting:
- make your verilog DUT test more smart☆22Sep 9, 2016Updated 9 years ago
- ☆16Apr 21, 2019Updated 6 years ago
- DUTH RISC-V Superscalar Microprocessor☆33Oct 23, 2024Updated last year
- Support code for DVCon 2021 paper submission☆12Mar 1, 2021Updated 4 years ago
- Useful UVM extensions☆27Jul 10, 2024Updated last year
- A RISC-V Symmetric Multiprocessor(SMP) based on TileLink and can run Linux OS☆34Oct 23, 2025Updated 3 months ago
- UVM clock agent which frequency, duty cycle can be configured, clock slow and gating function are also available☆10Aug 24, 2020Updated 5 years ago
- An out-of-order, dual issueed RISC-V core and SOC, a working project.☆10Apr 24, 2023Updated 2 years ago
- UVM register utility generation by inputting xls table☆39Aug 22, 2023Updated 2 years ago
- Connecting SystemC with SystemVerilog☆42Mar 25, 2012Updated 13 years ago
- RISC-V CPU in SystemVerilog & Custom Migen-based SoC Generator☆10Dec 29, 2021Updated 4 years ago
- RTL implementation of a ray-tracing GPU☆15Dec 18, 2012Updated 13 years ago
- Hardware Design, Exploration, and Code Generation for SoC Designers☆12Dec 15, 2019Updated 6 years ago
- SCARV: a side-channel hardened RISC-V platform☆28Jan 11, 2023Updated 3 years ago
- Systemverilog DPI-C call Python function☆28Mar 11, 2021Updated 4 years ago
- Chisel implementation of Neural Processing Unit for System on the Chip☆26Jan 19, 2026Updated 3 weeks ago
- HDLGen is an HDL generation tool, supporting embedded Perl or Python script, reduce manual work & improve effiency with a few embedded f…☆110Oct 31, 2023Updated 2 years ago
- AXI DMA Check: A utility to measure DMA speeds in simulation☆15Jan 22, 2025Updated last year
- OpenExSys_CoherentCache a directory-based MESI protocol coherent cache IP.☆21Mar 25, 2025Updated 10 months ago
- Implementation of the Snappy compression algorithm as a RoCC accelerator☆12Jul 29, 2019Updated 6 years ago
- Various low power labs using sky130☆13Sep 3, 2021Updated 4 years ago
- Common Agent is a generic agent implemented in SystemVerilog, based on UVM methodology, which can be easily extended to create very fast …☆13Apr 29, 2015Updated 10 years ago
- Quad SPI Flash XIP Controller with a direct mapped cache☆12Dec 9, 2020Updated 5 years ago
- Designed a pipelined calculation engine to read input/weights of neuron and compute/store results in SystemVerilog. Implemented fabric to…☆12Feb 12, 2019Updated 7 years ago
- MIAOW2.0 FPGA implementable design☆12Oct 18, 2017Updated 8 years ago
- Using Nim to interface with SystemVerilog test benches via DPI-C☆32May 15, 2025Updated 9 months ago
- A DMA Controller for RISCV CPUs☆13Aug 10, 2015Updated 10 years ago
- UVM Auto Generate ; Verify Project Build; Verilog Instance☆35Apr 15, 2020Updated 5 years ago
- SoC Based on ARM Cortex-M3☆37May 16, 2025Updated 9 months ago
- ☆14Apr 24, 2023Updated 2 years ago
- CNN accelerator using NoC architecture☆17Dec 6, 2018Updated 7 years ago
- For pre-silicon developers of RISC-V systems, riscv-vip is a SystemVerilog project that helps with pre-si verification and debug☆65Jan 13, 2021Updated 5 years ago
- A reliable, real-time subsystem for the Carfield SoC☆18Dec 2, 2025Updated 2 months ago
- IPs for data-plane integration of Hardware Processing Engines (HWPEs) within a PULP system☆21Jan 17, 2026Updated 3 weeks ago
- Parametric floating-point unit with support for standard RISC-V formats and operations as well as transprecision formats.☆18Nov 13, 2025Updated 3 months ago
- Universal Hardware Data Model. A complete modeling of the IEEE SystemVerilog Object Model with VPI Interface, Elaborator, Serialization, …☆18Sep 6, 2025Updated 5 months ago
- Generate a Verilog Source file and testbench file for a given Moore FSM☆17Nov 18, 2012Updated 13 years ago
- CS533 Course Project (ongoing) - Exploring Parallel Architectures for Neural Processing Unit Implementations☆20May 4, 2017Updated 8 years ago
- SPIR-V fragment shader GPU core based on RISC-V☆43May 26, 2021Updated 4 years ago