chad-q / andes-vector-riscv-dvLinks
Andes Vector Extension support added to riscv-dv
☆17Updated 5 years ago
Alternatives and similar repositories for andes-vector-riscv-dv
Users that are interested in andes-vector-riscv-dv are comparing it to the libraries listed below
Sorting:
- SystemVerilog Functional Coverage for RISC-V ISA☆29Updated last month
- verification of simple axi-based cache☆18Updated 6 years ago
- CORE-V MCU UVM Environment and Test Bench☆21Updated 11 months ago
- work in SSRL, SOC/NOC/Chiplet Design, DDR/UCIe/PCIe, UVM Framework☆34Updated 2 years ago
- ☆20Updated 5 years ago
- General Purpose AXI Direct Memory Access☆53Updated last year
- ☆21Updated 5 years ago
- Multi-Processor System on Chip verified with UVM/OSVVM/FV☆32Updated last month
- Various low power labs using sky130☆12Updated 3 years ago
- SoC Based on ARM Cortex-M3☆32Updated last month
- ☆30Updated this week
- ☆12Updated last year
- DUTH RISC-V Microprocessor☆20Updated 7 months ago
- DDR5 PHY Graduation project (Verification Team) under supervision of Si-Vision☆58Updated last year
- Contains commonly used UVM components (agents, environments and tests).☆29Updated 6 years ago
- Platform Level Interrupt Controller☆41Updated last year
- SystemVerilog modules and classes commonly used for verification☆50Updated 6 months ago
- Useful UVM extensions☆24Updated last year
- ☆20Updated 2 years ago
- DUTH RISC-V Superscalar Microprocessor☆31Updated 8 months ago
- AXI3 Bus Functional Models (Initiator & Target)☆29Updated 2 years ago
- HW-SW Co-Simulation Library for AMBA AXI BFM using DPI/VPI☆32Updated 6 months ago
- UVM Auto Generate ; Verify Project Build; Verilog Instance☆34Updated 5 years ago
- ☆29Updated 4 years ago
- LCAI-TIHU HW is an AI inference processor which is comprised of RISC-V cpu, nvdla, NoC bus, PCIe module, DDR, SRAM, bootROM, DMA and peri…☆41Updated 2 years ago
- 128KB AXI cache (32-bit in, 256-bit out)☆51Updated 4 years ago
- Synchronous FIFO design & verification using systemVerilog Assertions☆16Updated 3 years ago
- For pre-silicon developers of RISC-V systems, riscv-vip is a SystemVerilog project that helps with pre-si verification and debug☆60Updated 4 years ago
- make your verilog DUT test more smart☆22Updated 8 years ago
- Design and UVM-TB of RISC -V Microprocessor☆23Updated last year