merledu / azadi-socLinks
Azadi (Freedom) is a 32-bit RISC-V CPU based System on Chip.
☆32Updated last year
Alternatives and similar repositories for azadi-soc
Users that are interested in azadi-soc are comparing it to the libraries listed below
Sorting:
- DUTH RISC-V Superscalar Microprocessor☆31Updated 8 months ago
- Technology dependent cells instantiated in the design for generic process (simulation, FPGA)☆61Updated 5 months ago
- SystemVerilog Functional Coverage for RISC-V ISA☆28Updated 3 weeks ago
- Multi-Processor System on Chip verified with UVM/OSVVM/FV☆31Updated last month
- Design and UVM-TB of RISC -V Microprocessor☆23Updated last year
- LCAI-TIHU HW is an AI inference processor which is comprised of RISC-V cpu, nvdla, NoC bus, PCIe module, DDR, SRAM, bootROM, DMA and peri…☆39Updated 2 years ago
- [UNRELEASED] FP div/sqrt unit for transprecision☆22Updated last year
- ☆30Updated 2 months ago
- Implementation of the pipelined RISC V processor with many useful features as fully bypassing, dynamic branch prediction, single and mult…☆14Updated last year
- A 32 bit RISCV Based SOC with QSpi , Uart and 8 bit SDRAM Controller tagetted to efebless shuttle program☆20Updated 2 years ago
- A simple, scalable, source-synchronous, all-digital DDR link☆28Updated last week
- 100DaysofRTL & System Verilog design: basic logic gates, mux, half/full subtractor, Encoder, D flipflop, 8 bit counter, LFSR, Custom Coun…☆34Updated 2 years ago
- DMA Hardware Description with Verilog☆14Updated 5 years ago
- DDR4 Simulation Project in System Verilog☆41Updated 10 years ago
- Andes Vector Extension support added to riscv-dv☆17Updated 5 years ago
- 128KB AXI cache (32-bit in, 256-bit out)☆51Updated 4 years ago
- Simple single-port AXI memory interface☆41Updated last year
- ☆16Updated 6 years ago
- ASIC Design of the openSPARC Floating Point Unit☆13Updated 8 years ago
- Complete tutorial code.☆21Updated last year
- General Purpose AXI Direct Memory Access☆51Updated last year
- BlackParrot on Zynq☆42Updated 3 months ago
- A barebones 64-bit RISC-V micro-controller class CPU, implementing the I(nteger), M(ul/div), C(ompressed) and K(ryptography) extensions.☆44Updated 3 years ago
- The memory model was leveraged from micron.☆22Updated 7 years ago
- VSDBabySoC is a small mixed-signal SoC including PLL, DAC, and a RISCV-based processor named RVMYTH.☆43Updated 3 years ago
- CV32E40P is an in-order 4-stage RISC-V RV32IMFCXpulp CPU based on RI5CY from PULP-Platform☆19Updated last week
- SoCGen is a tool that automates SoC design by taking in a JSON description of the system and producing the final GDS-II. SoCGen supports …☆38Updated 4 years ago
- verification of simple axi-based cache☆18Updated 6 years ago
- Accelerating the AES algorithm on an FPGA and comparing the speedup with both AES and Modified AES algorithms☆27Updated 3 years ago
- SoC Based on ARM Cortex-M3☆32Updated last month