merledu / azadi-socLinks
Azadi (Freedom) is a 32-bit RISC-V CPU based System on Chip.
☆32Updated 2 years ago
Alternatives and similar repositories for azadi-soc
Users that are interested in azadi-soc are comparing it to the libraries listed below
Sorting:
- A barebones 64-bit RISC-V micro-controller class CPU, implementing the I(nteger), M(ul/div), C(ompressed) and K(ryptography) extensions.☆46Updated 3 years ago
- IEEE 754 single and double precision floating point library in systemverilog and vhdl☆68Updated 8 months ago
- HW-SW Co-Simulation Library for AMBA AXI BFM using DPI/VPI☆35Updated 8 months ago
- 256-bit vector processor based on the RISC-V vector (V) extension☆30Updated 4 years ago
- BlackParrot on Zynq☆45Updated 5 months ago
- LCAI-TIHU HW is an AI inference processor which is comprised of RISC-V cpu, nvdla, NoC bus, PCIe module, DDR, SRAM, bootROM, DMA and peri…☆42Updated 2 years ago
- Multi-Processor System on Chip verified with UVM/OSVVM/FV☆34Updated 3 months ago
- Design and UVM-TB of RISC -V Microprocessor☆25Updated last year
- DUTH RISC-V Superscalar Microprocessor☆31Updated 10 months ago
- ☆30Updated last week
- Implementation of the pipelined RISC V processor with many useful features as fully bypassing, dynamic branch prediction, single and mult…☆14Updated last year
- DMA Hardware Description with Verilog☆16Updated 5 years ago
- SystemVerilog Functional Coverage for RISC-V ISA☆30Updated 2 months ago
- Technology dependent cells instantiated in the design for generic process (simulation, FPGA)☆65Updated 7 months ago
- General Purpose AXI Direct Memory Access☆58Updated last year
- [UNRELEASED] FP div/sqrt unit for transprecision☆24Updated last year
- CV32E40P is an in-order 4-stage RISC-V RV32IMFCXpulp CPU based on RI5CY from PULP-Platform☆19Updated last month
- VSDBabySoC is a small mixed-signal SoC including PLL, DAC, and a RISCV-based processor named RVMYTH.☆44Updated 3 years ago
- This repo contain the PY-UVM Framework for different RISC-V Cores☆32Updated last year
- ☆29Updated 5 years ago
- The memory model was leveraged from micron.☆22Updated 7 years ago
- Digital Hardware Modelling using VHDL, Verilog, SystemVerilog, SystemC, HLS(C++, OpenCL)☆66Updated 6 months ago
- Pequeno (PQR5) is a 5-stage pipelined in-order RISC-V CPU Core compliant with RV32I ISA.☆112Updated this week
- Synopsys Design compiler, VCS and Tetra-MAX☆19Updated 7 years ago
- Implementation of the PCIe physical layer☆48Updated last month
- RISCV core RV32I/E.4 threads in a ring architecture☆32Updated 2 years ago
- Platform Level Interrupt Controller☆41Updated last year
- Accelerating the AES algorithm on an FPGA and comparing the speedup with both AES and Modified AES algorithms☆29Updated 3 years ago
- A Verilog implementation of a processor cache.☆28Updated 7 years ago
- Skid Buffer and Pipeline Skid Buffer designed in Verilog/System Verilog.☆22Updated last year