martinriis / RISC-V-Vector-ProcessorLinks
256-bit vector processor based on the RISC-V vector (V) extension
☆30Updated 4 years ago
Alternatives and similar repositories for RISC-V-Vector-Processor
Users that are interested in RISC-V-Vector-Processor are comparing it to the libraries listed below
Sorting:
- Azadi (Freedom) is a 32-bit RISC-V CPU based System on Chip.☆32Updated 2 years ago
- A barebones 64-bit RISC-V micro-controller class CPU, implementing the I(nteger), M(ul/div), C(ompressed) and K(ryptography) extensions.☆46Updated 3 years ago
- IEEE 754 single and double precision floating point library in systemverilog and vhdl☆69Updated 8 months ago
- General Purpose AXI Direct Memory Access☆58Updated last year
- Platform Level Interrupt Controller☆42Updated last year
- BlackParrot on Zynq☆46Updated 6 months ago
- Xilinx AXI VIP example of use☆42Updated 4 years ago
- Simple single-port AXI memory interface☆46Updated last year
- Two Level Cache Controller implementation in Verilog HDL☆52Updated 5 years ago
- SystemVerilog modules and classes commonly used for verification☆50Updated 8 months ago
- Prototype-network-on-chip (ProNoC) is an EDA tool that facilitates prototyping of custom heterogeneous NoC-based many-core-SoC (MCSoC).☆59Updated last month
- Design of 1024x32 SRAM (32Kbits) using OpenRAM and SKY130 PDKs with operating voltage of 1.8V and access time < 2.5ns☆76Updated 4 years ago
- ☆29Updated 3 weeks ago
- LCAI-TIHU HW is an AI inference processor which is comprised of RISC-V cpu, nvdla, NoC bus, PCIe module, DDR, SRAM, bootROM, DMA and peri…☆42Updated 2 years ago
- ☆64Updated 4 years ago
- RISCV model for Verilator/FPGA targets☆53Updated 5 years ago
- A simple DDR3 memory controller☆59Updated 2 years ago
- PCI Express controller model☆65Updated 2 years ago
- Repository gathering basic modules for CDC purpose☆54Updated 5 years ago
- 128KB AXI cache (32-bit in, 256-bit out)☆53Updated 4 years ago
- Parameterised Asynchronous AHB3-Lite to APB4 Bridge.☆45Updated last year
- Digital Hardware Modelling using VHDL, Verilog, SystemVerilog, SystemC, HLS(C++, OpenCL)☆66Updated 7 months ago
- EE 260 Winter 2017: Advanced VLSI Design☆66Updated 8 years ago
- RTL Verilog library for various DSP modules☆90Updated 3 years ago
- Implementing Different Adder Structures in Verilog☆72Updated 6 years ago
- RTL sources of the High-Performance L1 Dcache (HPDcache) for OpenHW CV cores☆90Updated 3 weeks ago
- The memory model was leveraged from micron.☆22Updated 7 years ago
- RISC-V Verification Interface☆103Updated 3 months ago
- ☆29Updated 5 years ago
- Generic FIFO implementation with optional FWFT☆60Updated 5 years ago