martinriis / RISC-V-Vector-ProcessorLinks
256-bit vector processor based on the RISC-V vector (V) extension
☆29Updated 4 years ago
Alternatives and similar repositories for RISC-V-Vector-Processor
Users that are interested in RISC-V-Vector-Processor are comparing it to the libraries listed below
Sorting:
- General Purpose AXI Direct Memory Access☆50Updated last year
- DMA Hardware Description with Verilog☆14Updated 5 years ago
- IEEE 754 single and double precision floating point library in systemverilog and vhdl☆65Updated 5 months ago
- Xilinx AXI VIP example of use☆40Updated 4 years ago
- A barebones 64-bit RISC-V micro-controller class CPU, implementing the I(nteger), M(ul/div), C(ompressed) and K(ryptography) extensions.☆44Updated 3 years ago
- AXI4 and AXI4-Lite interface definitions☆94Updated 4 years ago
- Prototype-network-on-chip (ProNoC) is an EDA tool that facilitates prototyping of custom heterogeneous NoC-based many-core-SoC (MCSoC).☆56Updated last week
- ☆30Updated last year
- ☆14Updated 2 years ago
- Platform Level Interrupt Controller☆40Updated last year
- 100DaysofRTL & System Verilog design: basic logic gates, mux, half/full subtractor, Encoder, D flipflop, 8 bit counter, LFSR, Custom Coun…☆34Updated 2 years ago
- ☆33Updated 6 years ago
- Generic FIFO implementation with optional FWFT☆57Updated 5 years ago
- Python Tool for UVM Testbench Generation☆52Updated last year
- Design of 1024x32 SRAM (32Kbits) using OpenRAM and SKY130 PDKs with operating voltage of 1.8V and access time < 2.5ns☆69Updated 4 years ago
- 128KB AXI cache (32-bit in, 256-bit out)☆49Updated 4 years ago
- SoC Based on ARM Cortex-M3☆32Updated 2 weeks ago
- RTL sources of the High-Performance L1 Dcache (HPDcache) for OpenHW CV cores☆77Updated this week
- Implementation of the pipelined RISC V processor with many useful features as fully bypassing, dynamic branch prediction, single and mult…☆14Updated last year
- RISC-V Verification Interface☆92Updated this week
- Accelerating the AES algorithm on an FPGA and comparing the speedup with both AES and Modified AES algorithms☆27Updated 3 years ago
- Simple single-port AXI memory interface☆41Updated 11 months ago
- Two Level Cache Controller implementation in Verilog HDL☆48Updated 4 years ago
- ☆58Updated 4 years ago
- SystemVerilog modules and classes commonly used for verification☆48Updated 4 months ago
- BlackParrot on Zynq☆41Updated 3 months ago
- Technology dependent cells instantiated in the design for generic process (simulation, FPGA)☆60Updated 4 months ago
- I present a novel pipelined fast Fourier transform (FFT) architecture which is capable of producing the output sequence in normal order. …☆42Updated last year
- ☆25Updated 3 years ago
- A Verilog implementation of a processor cache.☆25Updated 7 years ago