martinriis / RISC-V-Vector-Processor
256-bit vector processor based on the RISC-V vector (V) extension
☆28Updated 3 years ago
Alternatives and similar repositories for RISC-V-Vector-Processor:
Users that are interested in RISC-V-Vector-Processor are comparing it to the libraries listed below
- IEEE 754 single and double precision floating point library in systemverilog and vhdl☆62Updated 3 months ago
- General Purpose AXI Direct Memory Access☆49Updated 10 months ago
- A barebones 64-bit RISC-V micro-controller class CPU, implementing the I(nteger), M(ul/div), C(ompressed) and K(ryptography) extensions.☆44Updated 3 years ago
- AXI4 and AXI4-Lite interface definitions☆93Updated 4 years ago
- Prototype-network-on-chip (ProNoC) is an EDA tool that facilitates prototyping of custom heterogeneous NoC-based many-core-SoC (MCSoC).☆52Updated last week
- Vector processor for RISC-V vector ISA☆116Updated 4 years ago
- RISCV model for Verilator/FPGA targets☆50Updated 5 years ago
- 128KB AXI cache (32-bit in, 256-bit out)☆48Updated 3 years ago
- SystemVerilog modules and classes commonly used for verification☆46Updated 2 months ago
- 100DaysofRTL & System Verilog design: basic logic gates, mux, half/full subtractor, Encoder, D flipflop, 8 bit counter, LFSR, Custom Coun…☆34Updated 2 years ago
- SpinalHDL based, FPGA Suitable RTL Implementation of RISC-V RV32. Aligned with RISC-V Virtual Prototype☆45Updated 5 months ago
- ☆13Updated 2 years ago
- a hardware design library based on SpinalHDL, especially for stream processing operators on Xilinx FPGAs for Arithmetic, DSP, Communicati…☆59Updated last year
- Implementation of the pipelined RISC V processor with many useful features as fully bypassing, dynamic branch prediction, single and mult…☆14Updated last year
- Xilinx AXI VIP example of use☆34Updated 3 years ago
- The memory model was leveraged from micron.☆22Updated 7 years ago
- This repository is dedicated to providing a comprehensive guide and practical examples for using VC Formal for formal verification. Our g…☆18Updated last year
- Digital Hardware Modelling using VHDL, Verilog, SystemVerilog, SystemC, HLS(C++, OpenCL)☆63Updated last month
- Complete tutorial code.☆17Updated 10 months ago
- AXI3 Bus Functional Models (Initiator & Target)☆28Updated 2 years ago
- Two Level Cache Controller implementation in Verilog HDL☆41Updated 4 years ago
- RTL sources of the High-Performance L1 Dcache (HPDcache) for OpenHW CV cores☆68Updated last week
- Asynchronous fifo in verilog☆33Updated 9 years ago
- Platform Level Interrupt Controller☆37Updated 10 months ago
- Source code of the paper "Low-Cost and Programmable CRC Implementation based on FPGA"☆42Updated 4 years ago
- A PULP SoC for education, easy to understand and extend with a full flow for a physical design.☆65Updated this week
- CV32E40P is an in-order 4-stage RISC-V RV32IMFCXpulp CPU based on RI5CY from PULP-Platform☆19Updated 3 weeks ago
- ☆31Updated 5 years ago
- DUTH RISC-V Superscalar Microprocessor☆30Updated 5 months ago
- ☆25Updated 4 years ago