martinriis / RISC-V-Vector-ProcessorLinks
256-bit vector processor based on the RISC-V vector (V) extension
☆31Updated 4 years ago
Alternatives and similar repositories for RISC-V-Vector-Processor
Users that are interested in RISC-V-Vector-Processor are comparing it to the libraries listed below
Sorting:
- A barebones 64-bit RISC-V micro-controller class CPU, implementing the I(nteger), M(ul/div), C(ompressed) and K(ryptography) extensions.☆48Updated 3 years ago
- IEEE 754 single and double precision floating point library in systemverilog and vhdl☆80Updated last week
- ☆33Updated last month
- BlackParrot on Zynq☆47Updated 3 weeks ago
- Digital Hardware Modelling using VHDL, Verilog, SystemVerilog, SystemC, HLS(C++, OpenCL)☆68Updated 11 months ago
- Azadi (Freedom) is a 32-bit RISC-V CPU based System on Chip.☆32Updated 2 years ago
- General Purpose AXI Direct Memory Access☆62Updated last year
- Platform Level Interrupt Controller☆43Updated last year
- AXI Adapter(s) for RISC-V Atomic Operations☆66Updated last month
- Design and UVM-TB of RISC -V Microprocessor☆32Updated last year
- Xilinx AXI VIP example of use☆43Updated 4 years ago
- Verilog implementation of a 4-way Set associative cache with a write buffer (write) policy and FIFO replacement policy☆41Updated 9 years ago
- RISCV model for Verilator/FPGA targets☆53Updated 6 years ago
- A simple DDR3 memory controller☆61Updated 3 years ago
- ☆40Updated last year
- DMA Hardware Description with Verilog☆18Updated 6 years ago
- RISC-V Nox core☆71Updated 5 months ago
- The CORE-V CVA5 is an Application class 5-stage RISC-V CPU specifically targetting FPGA implementations.☆124Updated 6 months ago
- PCI Express controller model☆71Updated 3 years ago
- Accelerating the AES algorithm on an FPGA and comparing the speedup with both AES and Modified AES algorithms☆33Updated 4 years ago
- SystemVerilog Direct Programming Interface (DPI) Tutorial☆76Updated 5 years ago
- Hamming ECC Encoder and Decoder to protect memories☆34Updated 11 months ago
- Simple single-port AXI memory interface☆49Updated last year
- Two Level Cache Controller implementation in Verilog HDL☆56Updated 5 years ago
- Basic floating-point components for RISC-V processors☆67Updated 6 years ago
- Design of 1024x32 SRAM (32Kbits) using OpenRAM and SKY130 PDKs with operating voltage of 1.8V and access time < 2.5ns☆81Updated 4 years ago
- RTL sources of the High-Performance L1 Dcache (HPDcache) for OpenHW CV cores☆94Updated last month
- ☆70Updated 4 years ago
- A simple, scalable, source-synchronous, all-digital DDR link☆33Updated last month
- Implementing Different Adder Structures in Verilog☆76Updated 6 years ago