martinriis / RISC-V-Vector-ProcessorLinks
256-bit vector processor based on the RISC-V vector (V) extension
☆30Updated 4 years ago
Alternatives and similar repositories for RISC-V-Vector-Processor
Users that are interested in RISC-V-Vector-Processor are comparing it to the libraries listed below
Sorting:
- IEEE 754 single and double precision floating point library in systemverilog and vhdl☆70Updated 9 months ago
- General Purpose AXI Direct Memory Access☆59Updated last year
- Hamming ECC Encoder and Decoder to protect memories☆34Updated 8 months ago
- A barebones 64-bit RISC-V micro-controller class CPU, implementing the I(nteger), M(ul/div), C(ompressed) and K(ryptography) extensions.☆47Updated 3 years ago
- OpTiMSoC - A tiled SoC platform with a mesh NoC and OpenRISC CPU cores☆85Updated 4 years ago
- RISCV model for Verilator/FPGA targets☆53Updated 5 years ago
- AXI3 Bus Functional Models (Initiator & Target)☆29Updated 2 years ago
- Platform Level Interrupt Controller☆43Updated last year
- Two Level Cache Controller implementation in Verilog HDL☆52Updated 5 years ago
- BlackParrot on Zynq☆47Updated 7 months ago
- Azadi (Freedom) is a 32-bit RISC-V CPU based System on Chip.☆32Updated 2 years ago
- ☆40Updated last year
- Generic FIFO implementation with optional FWFT☆60Updated 5 years ago
- Basic floating-point components for RISC-V processors☆66Updated 5 years ago
- DMA Hardware Description with Verilog☆17Updated 5 years ago
- 128KB AXI cache (32-bit in, 256-bit out)☆53Updated 4 years ago
- Digital Hardware Modelling using VHDL, Verilog, SystemVerilog, SystemC, HLS(C++, OpenCL)☆67Updated 7 months ago
- Xilinx AXI VIP example of use☆42Updated 4 years ago
- Simple single-port AXI memory interface☆46Updated last year
- AXI4 and AXI4-Lite interface definitions☆96Updated 5 years ago
- LCAI-TIHU HW is an AI inference processor which is comprised of RISC-V cpu, nvdla, NoC bus, PCIe module, DDR, SRAM, bootROM, DMA and peri…☆42Updated 2 years ago
- Verilog implementation of a 4-way Set associative cache with a write buffer (write) policy and FIFO replacement policy☆41Updated 8 years ago
- RISC-V Nox core☆68Updated 2 months ago
- The memory model was leveraged from micron.☆24Updated 7 years ago
- EE 260 Winter 2017: Advanced VLSI Design☆66Updated 8 years ago
- Parameterised Asynchronous AHB3-Lite to APB4 Bridge.☆45Updated last year
- ☆67Updated 4 years ago
- Prototype-network-on-chip (ProNoC) is an EDA tool that facilitates prototyping of custom heterogeneous NoC-based many-core-SoC (MCSoC).☆59Updated this week
- SystemVerilog Direct Programming Interface (DPI) Tutorial☆70Updated 4 years ago
- A simple DDR3 memory controller☆59Updated 2 years ago