Alternatives and similar repositories for YuQuan

Users that are interested in YuQuan are comparing it to the libraries listed below

• tastynoob / aura-core
  "aura" my super-scalar O3 cpu core
  ☆24Updated last year
• FurryAcetylCoA / gtkwave-filter-process-RISC
  A tool to decode RISC-V and LoongArch and MIPS instructions in gtkwave
  ☆31Updated 8 months ago
• cyyself / soc-simulator
  A Verilator based SoC simulator that allows you to define AXI Slave interface in software.
  ☆50Updated 2 months ago
• OpenXiangShan / difftest
  Modern co-simulation framework for RISC-V CPUs
  ☆165Updated this week
• OSCPU-Zhoushan / Zhoushan
  Open Source Chip Project by University (OSCPU) - Zhoushan Core
  ☆54Updated 3 years ago
• XS-MLVP / picker
  Pick your favorite language to verify your chip.
  ☆74Updated this week
• LainChip / LainCore
  Linux-capable in-order superscaler LoongArch32r processor. Silicon-proven.
  ☆45Updated last year
• ftppz / ShanghaiTech-YSYX
  Unofficial guide for ysyx students applying to ShanghaiTech University
  ☆23Updated 9 months ago
• OpenXiangShan / gsim
  ☆63Updated 2 months ago
• chipsalliance / playground
  chipyard in mill :P
  ☆77Updated 2 years ago
• meow-chip / MeowV64
  A superscalar RISC-V CPU with out-of-order execution and multi-core support
  ☆61Updated 3 years ago
• XS-MLVP / UnityChipForXiangShan
  Crowdsourced Verification Project (UnityChip Verification) for the Xiangshan Processor
  ☆46Updated last month
• OpenXiangShan / CoupledL2
  Open-source non-blocking L2 cache
  ☆50Updated this week
• lizhirui / DreamCoreV2
  ☆22Updated 2 years ago
• Kumonda221-CrO3 / gitlab-runner-vivado
  Vivado in GitLab-Runner for GitLab CI/CD
  ☆10Updated 3 years ago
• OSCPU / chisel-playground
  ☆68Updated 10 months ago
• OSCPU / ysyxSoC
  ☆91Updated 2 months ago
• Maxpicca-Li / CDIM
  CQU Dual Issue Machine
  ☆38Updated last year
• f0rm2l1n / riscv-simulator-guide
  RISC-V模拟器，相关硬件实现`riscv-isa-sim`以及模拟器pk, bbl的指导手册
  ☆53Updated 5 years ago
• sifferman / labs-with-cva6
  Advanced Architecture Labs with CVA6
  ☆71Updated last year
• aaronshappell / tage-predictor
  SystemVerilog implemention of the TAGE branch predictor
  ☆13Updated 4 years ago
• RISMicroDevices / CHIron
  Open-source AMBA CHI infrastructures (supporting Issue B, E.b)
  ☆30Updated this week
• chipsalliance / chisel-interface
  The 'missing header' for Chisel
  ☆22Updated 9 months ago
• OpenXiangShan / HuanCun
  Open-source high-performance non-blocking cache
  ☆92Updated 2 weeks ago
• OpenXiangShan / Deterload
  Xiangshan deterministic workloads generator
  ☆24Updated 7 months ago
• OpenXiangShan / GEM5
  ☆117Updated this week
• jiegec / rocket-chip-vcu128
  Run Rocket Chip on VCU128
  ☆30Updated 2 months ago
• chipsalliance / riscv-vector-tests
  Unit tests generator for RVV 1.0
  ☆98Updated last month
• CherrySprings / CherrySprings
  ☆19Updated 2 years ago
• lizhirui / DreamCore
  ☆64Updated 3 years ago