Alternatives and similar repositories for YuQuan

Users that are interested in YuQuan are comparing it to the libraries listed below

• tastynoob / aura-core
  "aura" my super-scalar O3 cpu core
  ☆24Updated last year
• FurryAcetylCoA / gtkwave-filter-process-RISC
  A tool to decode RISC-V and LoongArch and MIPS instructions in gtkwave
  ☆31Updated 2 months ago
• cyyself / soc-simulator
  A Verilator based SoC simulator that allows you to define AXI Slave interface in software.
  ☆49Updated 8 months ago
• OSCPU-Zhoushan / Zhoushan
  Open Source Chip Project by University (OSCPU) - Zhoushan Core
  ☆51Updated 2 years ago
• OpenXiangShan / difftest
  Modern co-simulation framework for RISC-V CPUs
  ☆147Updated this week
• meow-chip / MeowV64
  A superscalar RISC-V CPU with out-of-order execution and multi-core support
  ☆62Updated 3 years ago
• XS-MLVP / picker
  Pick your favorite language to verify your chip.
  ☆51Updated this week
• sifferman / labs-with-cva6
  Advanced Architecture Labs with CVA6
  ☆64Updated last year
• f0rm2l1n / riscv-simulator-guide
  RISC-V模拟器，相关硬件实现`riscv-isa-sim`以及模拟器pk, bbl的指导手册
  ☆52Updated 5 years ago
• CherrySprings / CherrySprings
  ☆18Updated 2 years ago
• sequencer / arithmetic
  ☆33Updated 3 months ago
• LainChip / LainCore
  Linux-capable in-order superscaler LoongArch32r processor. Silicon-proven.
  ☆42Updated 11 months ago
• chipsalliance / chisel-interface
  The 'missing header' for Chisel
  ☆20Updated 3 months ago
• OSCPU / chisel-playground
  ☆67Updated 5 months ago
• Kumonda221-CrO3 / gitlab-runner-vivado
  Vivado in GitLab-Runner for GitLab CI/CD
  ☆10Updated 2 years ago
• Maxpicca-Li / CDIM
  CQU Dual Issue Machine
  ☆35Updated last year
• ljwljwljwljw / DiplomaticBackend
  ☆17Updated 3 years ago
• lizhirui / DreamCoreV2
  ☆22Updated 2 years ago
• ftppz / ShanghaiTech-YSYX
  Unofficial guide for ysyx students applying to ShanghaiTech University
  ☆21Updated 4 months ago
• chipsalliance / playground
  chipyard in mill :P
  ☆78Updated last year
• jiegec / rocket-chip-vcu128
  Run Rocket Chip on VCU128
  ☆30Updated 7 months ago
• OpenXiangShan / Deterload
  Xiangshan deterministic workloads generator
  ☆19Updated last month
• aaronshappell / tage-predictor
  SystemVerilog implemention of the TAGE branch predictor
  ☆12Updated 4 years ago
• OSCPU / ysyxSoC
  ☆86Updated 2 months ago
• OpenXiangShan / gsim
  ☆39Updated this week
• yamak / axi-nodes
  ☆19Updated 3 years ago
• OpenXiangShan / fudian
  Open source high performance IEEE-754 floating unit
  ☆77Updated last year
• OSCPU / yosys-sta
  ☆72Updated 2 months ago
• chipsalliance / riscv-vector-tests
  Unit tests generator for RVV 1.0
  ☆88Updated last month
• chipsalliance / espresso
  ☆40Updated last month