Tang-Haojin / YuQuan
A RISC-V core running Debian (and a LoongArch core running Linux).
☆22Updated last year
Alternatives and similar repositories for YuQuan:
Users that are interested in YuQuan are comparing it to the libraries listed below
- "aura" my super-scalar O3 cpu core☆24Updated 10 months ago
- A tool to decode RISC-V and LoongArch and MIPS instructions in gtkwave☆30Updated 11 months ago
- A Verilator based SoC simulator that allows you to define AXI Slave interface in software.☆48Updated 4 months ago
- ☆63Updated last month
- Open Source Chip Project by University (OSCPU) - Zhoushan Core☆49Updated 2 years ago
- The 'missing header' for Chisel☆18Updated this week
- ☆19Updated this week
- ☆32Updated this week
- ☆79Updated last month
- Open-source high-performance RISC-V processor☆28Updated 2 weeks ago
- ☆74Updated this week
- ☆62Updated 3 months ago
- Unofficial guide for ysyx students applying to ShanghaiTech University☆21Updated last month
- ☆22Updated last year
- Linux-capable in-order superscaler LoongArch32r processor. Silicon-proven.☆38Updated 8 months ago
- Pick your favorite language to verify your chip.☆41Updated 2 weeks ago
- The Scala parser to parse riscv/riscv-opcodes generate☆15Updated this week
- RISC-V模拟器,相关硬件实现`riscv-isa-sim`以及模拟器pk, bbl的指导手册☆52Updated 4 years ago
- ☆17Updated 3 years ago
- Open-source non-blocking L2 cache☆37Updated this week
- ☆17Updated last year
- ☆11Updated last month
- SystemVerilog implemention of the TAGE branch predictor☆11Updated 3 years ago
- ☆63Updated 7 months ago
- Modern co-simulation framework for RISC-V CPUs☆139Updated this week
- NSCSCC 2023 The Second Prize. TEAM PUA FROM HDU.☆11Updated 11 months ago
- Advanced Architecture Labs with CVA6☆55Updated last year
- Highly configurable out-of-order MIPS32 processor, capable of booting Linux.☆38Updated last year
- Xiangshan deterministic workloads generator☆17Updated 3 weeks ago
- ☆19Updated last week