Tang-Haojin / YuQuan
A RISC-V core running Debian (and a LoongArch core running Linux).
☆22Updated 11 months ago
Alternatives and similar repositories for YuQuan:
Users that are interested in YuQuan are comparing it to the libraries listed below
- "aura" my super-scalar O3 cpu core☆24Updated 8 months ago
- A tool to decode RISC-V and LoongArch and MIPS instructions in gtkwave☆28Updated 10 months ago
- A Verilator based SoC simulator that allows you to define AXI Slave interface in software.☆46Updated 3 months ago
- ☆59Updated 2 weeks ago
- Open Source Chip Project by University (OSCPU) - Zhoushan Core☆49Updated 2 years ago
- Unofficial guide for ysyx students applying to ShanghaiTech University☆21Updated this week
- ☆79Updated last week
- ☆32Updated this week
- The Scala parser to parse riscv/riscv-opcodes generate☆13Updated 2 weeks ago
- The 'missing header' for Chisel☆18Updated this week
- Linux-capable in-order superscaler LoongArch32r processor. Silicon-proven.☆38Updated 6 months ago
- ☆17Updated 2 years ago
- ☆11Updated last week
- Advanced Architecture Labs with CVA6☆54Updated last year
- ☆53Updated last month
- ☆21Updated last year
- ☆17Updated last year
- Open-source high-performance RISC-V processor☆27Updated last month
- Pick your favorite language to verify your chip.☆37Updated this week
- ☆74Updated this week
- chipyard in mill :P☆77Updated last year
- High performance LA32R out-of-order processor core. (NSCSCC 2023 Special Prize)☆74Updated last year
- Open-source non-blocking L2 cache☆35Updated this week
- Highly configurable out-of-order MIPS32 processor, capable of booting Linux.☆38Updated last year
- Modern co-simulation framework for RISC-V CPUs☆133Updated this week
- ☆63Updated 2 years ago
- Open-source high-performance non-blocking cache☆75Updated this week
- Unit tests generator for RVV 1.0☆75Updated 2 weeks ago