stillwater-sc / RISC-V-TensorCore
Transactional Verilog design and Verilator Testbench for a RISC-V TensorCore Vector co-processor for reproducible linear algebra
☆49Updated 3 years ago
Alternatives and similar repositories for RISC-V-TensorCore:
Users that are interested in RISC-V-TensorCore are comparing it to the libraries listed below
- Advanced Architecture Labs with CVA6☆54Updated last year
- RTL sources of the High-Performance L1 Dcache (HPDcache) for OpenHW CV cores☆64Updated this week
- A 32-bit RISC-V Processor Designed with High-Level Synthesis☆51Updated 4 years ago
- ☆40Updated 5 years ago
- ☆32Updated this week
- Prototype-network-on-chip (ProNoC) is an EDA tool that facilitates prototyping of custom heterogeneous NoC-based many-core-SoC (MCSoC).☆49Updated this week
- ☆25Updated 11 months ago
- A Style Guide for the Chisel Hardware Construction Language☆106Updated 3 years ago
- HLS for Networks-on-Chip☆33Updated 3 years ago
- a hardware design library based on SpinalHDL, especially for stream processing operators on Xilinx FPGAs for Arithmetic, DSP, Communicati…☆57Updated last year
- Pure digital components of a UCIe controller☆53Updated last week
- Vector processor for RISC-V vector ISA☆112Updated 4 years ago
- ☆24Updated 5 years ago
- ☆29Updated last month
- ☆27Updated 5 years ago
- Examples for creating AXI-interfaced peripherals in Chisel☆74Updated 9 years ago
- ☆50Updated 3 years ago
- vector multiplication adder accelerator (using chisel 3 and RocketChip RoCC ) 向量乘法累加加速器☆51Updated 4 years ago
- An example of using Ramulator as memory model in a cycle-accurate SystemC Design☆48Updated 7 years ago
- CHIPKIT: An agile, reusable open-source framework for rapid test chip development☆40Updated 4 years ago
- Spatz is a compact RISC-V-based vector processor meant for high-performance, small computing clusters.☆86Updated last week
- Heterogeneous Research Platform (HERO) for exploration of heterogeneous computers consisting of programmable many-core accelerators and a…☆98Updated last year
- A simple MIPS-like CPU demo in C++ for Xilinx Vivado HLS☆18Updated 5 years ago
- PiDRAM is the first flexible end-to-end framework that enables system integration studies and evaluation of real Processing-using-Memory …☆60Updated last year
- A Fast, Low-Overhead On-chip Network☆156Updated this week
- DUTH RISC-V Superscalar Microprocessor☆29Updated 3 months ago
- IEEE 754 single and double precision floating point library in systemverilog and vhdl☆61Updated last month
- A GPU acceleration flow for RTL simulation with batch stimulus☆99Updated 9 months ago
- Project repo for the POSH on-chip network generator☆43Updated last year
- CGRA-Flow is an integrated framework for CGRA compilation, exploration, synthesis, and development.☆118Updated last month