stillwater-sc / RISC-V-TensorCore
Transactional Verilog design and Verilator Testbench for a RISC-V TensorCore Vector co-processor for reproducible linear algebra
☆50Updated 3 years ago
Alternatives and similar repositories for RISC-V-TensorCore:
Users that are interested in RISC-V-TensorCore are comparing it to the libraries listed below
- Advanced Architecture Labs with CVA6☆54Updated last year
- RTL sources of the High-Performance L1 Dcache (HPDcache) for OpenHW CV cores☆64Updated last month
- ☆41Updated 6 years ago
- Prototype-network-on-chip (ProNoC) is an EDA tool that facilitates prototyping of custom heterogeneous NoC-based many-core-SoC (MCSoC).☆50Updated 2 weeks ago
- a hardware design library based on SpinalHDL, especially for stream processing operators on Xilinx FPGAs for Arithmetic, DSP, Communicati…☆58Updated last year
- HLS for Networks-on-Chip☆33Updated 4 years ago
- A Style Guide for the Chisel Hardware Construction Language☆107Updated 3 years ago
- PiDRAM is the first flexible end-to-end framework that enables system integration studies and evaluation of real Processing-using-Memory …☆62Updated last year
- Pure digital components of a UCIe controller☆55Updated this week
- A 32-bit RISC-V Processor Designed with High-Level Synthesis☆52Updated 5 years ago
- IEEE 754 single and double precision floating point library in systemverilog and vhdl☆61Updated 2 months ago
- General Purpose AXI Direct Memory Access☆48Updated 9 months ago
- Heterogeneous Research Platform (HERO) for exploration of heterogeneous computers consisting of programmable many-core accelerators and a…☆99Updated last year
- For contributions of Chisel IP to the chisel community.☆59Updated 3 months ago
- Examples for creating AXI-interfaced peripherals in Chisel☆74Updated 9 years ago
- A Fast, Low-Overhead On-chip Network☆178Updated this week
- DUTH RISC-V Superscalar Microprocessor☆30Updated 4 months ago
- Digital Hardware Modelling using VHDL, Verilog, SystemVerilog, SystemC, HLS(C++, OpenCL)☆63Updated 2 weeks ago
- AutoSVA is a tool to automatically generate formal testbenches for unit-level RTL verification. The goal is to, based on annotations made…☆76Updated 11 months ago
- Vector processor for RISC-V vector ISA☆113Updated 4 years ago
- Xilinx AXI VIP example of use☆34Updated 3 years ago
- A modular, parametrizable, and highly flexible Data Movement Accelerator (DMA)☆123Updated this week
- An almost empty chisel project as a starting point for hardware design☆30Updated last month
- AXI Adapter(s) for RISC-V Atomic Operations☆60Updated 6 months ago
- ☆12Updated 3 months ago
- RiftCore is a 9-stage, single-issue, out-of-order 64-bits RISC-V Core, which supports RV64IMC and 3-level Cache System☆37Updated 2 years ago
- ☆88Updated last year
- An energy-efficient RISC-V floating-point compute cluster.☆68Updated last week
- ☆37Updated 2 months ago
- Lectures for the Agile Hardware Design course in Jupyter Notebooks☆87Updated 11 months ago