stillwater-sc / RISC-V-TensorCore
Transactional Verilog design and Verilator Testbench for a RISC-V TensorCore Vector co-processor for reproducible linear algebra
☆54Updated 3 years ago
Alternatives and similar repositories for RISC-V-TensorCore
Users that are interested in RISC-V-TensorCore are comparing it to the libraries listed below
Sorting:
- Advanced Architecture Labs with CVA6☆59Updated last year
- ☆48Updated 6 years ago
- HLS for Networks-on-Chip☆34Updated 4 years ago
- TensorCore Vector Processor for Deep Learning - Google Summer of Code Project☆20Updated 3 years ago
- SAURIA (Systolic-Array tensor Unit for aRtificial Intelligence Acceleration) is an open-source Convolutional Neural Network accelerator b…☆41Updated 7 months ago
- PiDRAM is the first flexible end-to-end framework that enables system integration studies and evaluation of real Processing-using-Memory …☆66Updated last year
- RTL sources of the High-Performance L1 Dcache (HPDcache) for OpenHW CV cores☆72Updated 3 weeks ago
- CGRA-Flow is an integrated framework for CGRA compilation, exploration, synthesis, and development.☆127Updated last week
- A 32-bit RISC-V Processor Designed with High-Level Synthesis☆52Updated 5 years ago
- Project repo for the POSH on-chip network generator☆45Updated last month
- An integrated CGRA design framework☆88Updated last month
- An Open-Hardware CGRA for accelerated computation on the edge.☆25Updated 8 months ago
- Simulator framework for analysis of performance, energy consumption, area and cost of multi-node multi-chiplet tile-based manycore design…☆65Updated 10 months ago
- A Style Guide for the Chisel Hardware Construction Language☆107Updated 3 years ago
- ☆33Updated 6 years ago
- eyeriss-chisel3☆40Updated 3 years ago
- Public release☆51Updated 5 years ago
- Prototype-network-on-chip (ProNoC) is an EDA tool that facilitates prototyping of custom heterogeneous NoC-based many-core-SoC (MCSoC).☆56Updated 2 months ago
- Heterogeneous Research Platform (HERO) for exploration of heterogeneous computers consisting of programmable many-core accelerators and a…☆101Updated last year
- High-Performance Sparse Linear Algebra on HBM-Equipped FPGAs Using HLS☆90Updated 7 months ago
- An Open-Source Tool for CGRA Accelerators☆65Updated 3 weeks ago
- Contains FPGA benchmarks for Vivado HLS and Catapult HLS☆26Updated 4 years ago
- a hardware design library based on SpinalHDL, especially for stream processing operators on Xilinx FPGAs for Arithmetic, DSP, Communicati…☆62Updated last year
- A DSL for Systolic Arrays☆79Updated 6 years ago
- ☆27Updated 5 years ago
- cycle accurate Network-on-Chip Simulator☆27Updated 2 years ago
- Vector processor for RISC-V vector ISA☆117Updated 4 years ago
- CGRA framework with vectorization support.☆29Updated this week
- An example of using Ramulator as memory model in a cycle-accurate SystemC Design☆50Updated 7 years ago
- vector multiplication adder accelerator (using chisel 3 and RocketChip RoCC ) 向量乘法累加加速器☆53Updated 5 years ago