IBM / cmnncLinks
Computational Memory Neural Network Compiler
☆11Updated 4 years ago
Alternatives and similar repositories for cmnnc
Users that are interested in cmnnc are comparing it to the libraries listed below
Sorting:
- dMazeRunner: Dataflow acceleration optimization infrastructure for coarse-grained programmable accelerators☆47Updated 3 years ago
- Stencil with Optimized Dataflow Architecture Compiler☆17Updated 5 years ago
- ☆32Updated 4 years ago
- A reference implementation of the Mind Mappings Framework.☆30Updated 3 years ago
- ☆42Updated last year
- ☆29Updated 4 years ago
- [ICASSP'20] DNN-Chip Predictor: An Analytical Performance Predictor for DNN Accelerators with Various Dataflows and Hardware Architecture…☆25Updated 3 years ago
- Heterogenous ML accelerator☆19Updated 6 months ago
- Benchmark framework of compute-in-memory based accelerators for deep neural network (inference engine focused)☆22Updated 4 years ago
- Tool for optimize CNN blocking☆94Updated 5 years ago
- ☆71Updated 5 years ago
- A general framework for optimizing DNN dataflow on systolic array☆38Updated 4 years ago
- ☆72Updated 2 years ago
- Dynamically Reconfigurable Architecture Template and Cycle-level Microarchitecture Simulator for Dataflow AcCelerators☆30Updated 2 years ago
- ☆27Updated 5 years ago
- Fast Emulation of Approximate DNN Accelerators in PyTorch☆28Updated last year
- ☆28Updated 2 years ago
- MAERI: A DNN accelerator with reconfigurable interconnects to support flexible dataflow (http://synergy.ece.gatech.edu/tools/maeri/)☆65Updated 4 years ago
- Here are some implementations of basic hardware units in RTL language (verilog for now), which can be used for area/power evaluation and …☆12Updated 2 years ago
- ☆13Updated last year
- mRNA☆24Updated 4 years ago
- A scheduler for spatial DNN accelerators that generate high-performance schedules in one shot using mixed integer programming (MIP)☆83Updated 2 years ago
- Graph-learning assisted instruction vulnerability estimation published in DATE 2020☆14Updated 4 years ago
- Linux docker for the DNN accelerator exploration infrastructure composed of Accelergy and Timeloop☆59Updated last month
- ☆25Updated last year
- ☆35Updated 5 years ago
- A Unified Framework for Training, Mapping and Simulation of ReRAM-Based Convolutional Neural Network Acceleration☆35Updated 3 years ago
- ☆15Updated 5 years ago
- [FPGA'21] Microbenchmarks for Demystifying the Memory System of Modern Datacenter FPGAs for Software Programmers☆31Updated 3 years ago
- MICRO22 artifact evaluation for Sparseloop☆44Updated 3 years ago