Alternatives and similar repositories for cmnnc

Users that are interested in cmnnc are comparing it to the libraries listed below

• MPSLab-ASU / dMazeRunner
  dMazeRunner: Dataflow acceleration optimization infrastructure for coarse-grained programmable accelerators
  ☆47Updated 3 years ago
• UCLA-VAST / soda-compiler
  Stencil with Optimized Dataflow Architecture Compiler
  ☆17Updated 5 years ago
• neurosim / DNN_NeuroSim_V1.1
  Benchmark framework of compute-in-memory based accelerators for deep neural network (inference engine focused)
  ☆22Updated 4 years ago
• MPSLab-ASU / DiRAC
  Dynamically Reconfigurable Architecture Template and Cycle-level Microarchitecture Simulator for Dataflow AcCelerators
  ☆30Updated 2 years ago
• maeri-project / MAERI_bsv
  MAERI: A DNN accelerator with reconfigurable interconnects to support flexible dataflow (http://synergy.ece.gatech.edu/tools/maeri/)
  ☆67Updated 4 years ago
• GATECH-EIC / AutoDNNchip
  ☆71Updated 5 years ago
• kartik-hegde / mindmappings
  A reference implementation of the Mind Mappings Framework.
  ☆30Updated 4 years ago
• BradMcDanel / column-combine
  ☆27Updated 5 years ago
• xuanyoya / Interstellar-CNN-scheduler
  Tool for optimize CNN blocking
  ☆94Updated 5 years ago
• maestro-project / gamma
  ☆42Updated last year
• priyanka-raina / dnn-accelerator
  ☆15Updated 5 years ago
• maestro-project / confuciux
  ☆32Updated 4 years ago
• he-actlab / planaria.code
  ☆29Updated 4 years ago
• ucb-bar / cosa
  A scheduler for spatial DNN accelerators that generate high-performance schedules in one shot using mixed integer programming (MIP)
  ☆85Updated 2 years ago
• GATECH-EIC / DNN-Chip-Predictor
  [ICASSP'20] DNN-Chip Predictor: An Analytical Performance Predictor for DNN Accelerators with Various Dataflows and Hardware Architecture…
  ☆25Updated 3 years ago
• I-Doctor / RTL_library_of_basic_hardware_units
  Here are some implementations of basic hardware units in RTL language (verilog for now), which can be used for area/power evaluation and …
  ☆13Updated 2 years ago
• YulhwaKim / RRAMScalable_BNN
  Neural Network-Hardware Co-design for Scalable RRAM-based BNN Accelerators
  ☆11Updated 6 years ago
• UCLA-VAST / FlexCNN
  ☆72Updated 2 years ago
• elliothe / pytorx
  Neural Network Evaluation Tool on Crossbar-based Accelerator with Resistive Memory
  ☆42Updated 6 years ago
• scalesim-project / krittika
  Heterogenous ML accelerator
  ☆20Updated 9 months ago
• diwu1990 / uSystolic-Sim
  A systolic array simulator for multi-cycle MACs and varying-byte words, with the paper accepted to HPCA 2022.
  ☆84Updated 4 years ago
• Accelergy-Project / pytorch2timeloop-converter
  ☆13Updated last year
• Accelergy-Project / processing-in-memory-design
  ☆25Updated last year
• ucb-bar / MoCA
  ☆28Updated 2 years ago
• cornell-zhang / GLAIVE
  Graph-learning assisted instruction vulnerability estimation published in DATE 2020
  ☆14Updated 5 years ago
• horizon-research / systolic-array-dataflow-optimizer
  A general framework for optimizing DNN dataflow on systolic array
  ☆38Updated 5 years ago
• CRAFT-THU / XB-Sim
  A Unified Framework for Training, Mapping and Simulation of ReRAM-Based Convolutional Neural Network Acceleration
  ☆36Updated 3 years ago
• synergy-noc-generators / Proteus
  ☆10Updated 3 years ago
• Accelergy-Project / accelergy-timeloop-infrastructure
  Linux docker for the DNN accelerator exploration infrastructure composed of Accelergy and Timeloop
  ☆62Updated 3 months ago
• cwfletcher / buffets
  Implementations of Buffets, which are efficient, composable idioms for implementing Explicit Decoupled Data Orchestration.
  ☆82Updated 6 years ago