sld-columbia / esp-cachesLinks
SystemVerilog overhaul of ESP L2 and LLC caches with directory based protocol
☆17Updated 7 months ago
Alternatives and similar repositories for esp-caches
Users that are interested in esp-caches are comparing it to the libraries listed below
Sorting:
- ☆29Updated 2 weeks ago
- A DDR3 Controller that uses the Xilinx MIG-7 PHY to interface with DDR3 devices.☆11Updated 4 years ago
- ☆19Updated last month
- ☆27Updated 5 years ago
- Binary Single Precision Floating-point Fused Multiply-Add Unit Design (Verilog HDL)☆22Updated 12 years ago
- The official NaplesPU hardware code repository☆19Updated 6 years ago
- verification of simple axi-based cache☆18Updated 6 years ago
- DUTH RISC-V Superscalar Microprocessor☆31Updated 11 months ago
- APB Logic☆20Updated this week
- ☆29Updated 5 years ago
- Skid Buffer and Pipeline Skid Buffer designed in Verilog/System Verilog.☆22Updated last year
- HLS for Networks-on-Chip☆36Updated 4 years ago
- DUTH RISC-V Microprocessor☆22Updated 10 months ago
- ☆10Updated 3 years ago
- ☆13Updated 7 months ago
- Development of a Network on Chip Simulation using SystemC.☆34Updated 8 years ago
- HW-SW Co-Simulation Library for AMBA AXI BFM using DPI/VPI☆36Updated 9 months ago
- The RTL source for AnyCore RISC-V☆32Updated 3 years ago
- FPU Generator☆20Updated 4 years ago
- Functional Verification the MMU (Memory Management Unit) of a multiprocessor with Data Cache and Instruction Cache☆13Updated 9 years ago
- The ParaNut Processor - Highly Parallel and More Than Just a CPU Core☆36Updated 2 years ago
- Digital Hardware Modelling using VHDL, Verilog, SystemVerilog, SystemC, HLS(C++, OpenCL)☆67Updated 7 months ago
- ☆15Updated 3 years ago
- Andes Vector Extension support added to riscv-dv☆17Updated 5 years ago
- UVM testbench for verifying the Pulpino SoC☆14Updated 5 years ago
- LIS Network-on-Chip Implementation☆31Updated 9 years ago
- Network on Chip for MPSoC☆28Updated 4 months ago
- CS533 Course Project (ongoing) - Exploring Parallel Architectures for Neural Processing Unit Implementations☆19Updated 8 years ago
- Implementation of the pipelined RISC V processor with many useful features as fully bypassing, dynamic branch prediction, single and mult…☆15Updated last year
- RISC-V vector and tensor compute extensions for Vortex GPGPU acceleration for ML workloads. Optimized for transformer models, CNNs, and g…☆15Updated 5 months ago