Alternatives and similar repositories for esp-caches:

Users that are interested in esp-caches are comparing it to the libraries listed below

• hyoukjun / microswitch-noc
  ☆26Updated 5 years ago
• iammituraj / skid_buffer
  Skid Buffer and Pipeline Skid Buffer designed in Verilog/System Verilog.
  ☆18Updated 7 months ago
• pulp-platform / axi_llc
  ☆25Updated last week
• ic-lab-duth / DRIM-S
  DUTH RISC-V Superscalar Microprocessor
  ☆31Updated 5 months ago
• ic-lab-duth / NoCpad
  HLS for Networks-on-Chip
  ☆34Updated 4 years ago
• pulp-platform / apb
  APB Logic
  ☆17Updated 4 months ago
• loghall / axi_cache
  verification of simple axi-based cache
  ☆18Updated 5 years ago
• ljgibbslf / basic_cache_core
  ☆26Updated 4 years ago
• ic-lab-duth / DRIM
  DUTH RISC-V Microprocessor
  ☆18Updated 4 months ago
• chad-q / andes-vector-riscv-dv
  Andes Vector Extension support added to riscv-dv
  ☆14Updated 4 years ago
• nullromo / compression-accelerator
  Implementation of the Snappy compression algorithm as a RoCC accelerator
  ☆11Updated 5 years ago
• GuiZhaoCodeSource / Func_Verif_MMU_Code_Source
  Functional Verification the MMU (Memory Management Unit) of a multiprocessor with Data Cache and Instruction Cache
  ☆12Updated 9 years ago
• Liu-Cheng / cycle-accurate-SystemC-simulator-over-ramulator
  An example of using Ramulator as memory model in a cycle-accurate SystemC Design
  ☆49Updated 7 years ago
• ben-marshall / croyde-riscv
  A barebones 64-bit RISC-V micro-controller class CPU, implementing the I(nteger), M(ul/div), C(ompressed) and K(ryptography) extensions.
  ☆44Updated 3 years ago
• adki / cosim_bfm_library
  HW-SW Co-Simulation Library for AMBA AXI BFM using DPI/VPI
  ☆31Updated 3 months ago
• Nikola2444 / RISC-V-vector-processor
  ☆13Updated 2 years ago
• jessebarreto / NetworkOnChip
  Development of a Network on Chip Simulation using SystemC.
  ☆31Updated 7 years ago
• freecores / robust_axi_fabric
  Generic AXI interconnect fabric
  ☆13Updated 10 years ago
• vlsi-lab / len5
  LEN5 is a configurable, speculative, out-of-order, 64-bit RISC-V microprocessor targetting etherogeneus systems on chip.
  ☆16Updated 11 months ago
• kuladeepsaireddy / OpenNoc
  ☆31Updated 5 years ago
• ultraembedded / core_axi_cache
  128KB AXI cache (32-bit in, 256-bit out)
  ☆48Updated 3 years ago
• riscv-verification / riscvISACOV
  SystemVerilog Functional Coverage for RISC-V ISA
  ☆26Updated 6 months ago
• LCAI-TIHU / HW
  LCAI-TIHU HW is an AI inference processor which is comprised of RISC-V cpu, nvdla, NoC bus, PCIe module, DDR, SRAM, bootROM, DMA and peri…
  ☆36Updated 2 years ago
• yuhsuan-t / NPU-Architecture
  CS533 Course Project (ongoing) - Exploring Parallel Architectures for Neural Processing Unit Implementations
  ☆19Updated 7 years ago
• whatmough / CHIPKIT
  CHIPKIT: An agile, reusable open-source framework for rapid test chip development
  ☆41Updated 4 years ago
• AlessandroCilardo / NaplesPU
  The official NaplesPU hardware code repository
  ☆15Updated 5 years ago
• pulp-platform / quadrilatero
  matrix-coprocessor for RISC-V
  ☆13Updated 2 weeks ago
• THU-DSP-LAB / ventus-gpgpu-cpp-simulator
  Cycle-accurate C++ & SystemC simulator for the RISC-V GPGPU Ventus
  ☆25Updated last week
• embecosm / ri5cy
  The PULP RI5CY core modified for Verilator modeling and as a GDB server.
  ☆22Updated 6 years ago
• hsa-ees / paranut
  The ParaNut Processor - Highly Parallel and More Than Just a CPU Core
  ☆33Updated last year