sld-columbia / esp-cachesView external linksLinks
SystemVerilog overhaul of ESP L2 and LLC caches with directory based protocol
☆18Feb 27, 2025Updated 11 months ago
Alternatives and similar repositories for esp-caches
Users that are interested in esp-caches are comparing it to the libraries listed below
Sorting:
- Functional Verification the MMU (Memory Management Unit) of a multiprocessor with Data Cache and Instruction Cache☆13Nov 9, 2015Updated 10 years ago
- UVM components for DSP tasks (MODulation/DEModulation)☆14Mar 2, 2022Updated 3 years ago
- ☆21Dec 19, 2025Updated last month
- OpenExSys_NoC a mesh-based network on chip IP.☆20Dec 1, 2023Updated 2 years ago
- A simple cycle-accurate DaDianNao simulator☆13Mar 27, 2019Updated 6 years ago
- RTL implementation of a ray-tracing GPU☆15Dec 18, 2012Updated 13 years ago
- ☆11Jul 28, 2022Updated 3 years ago
- ☆10Apr 8, 2021Updated 4 years ago
- RISC-V vector and tensor compute extensions for Vortex GPGPU acceleration for ML workloads. Optimized for transformer models, CNNs, and g…☆21Apr 25, 2025Updated 9 months ago
- ☆33Nov 24, 2025Updated 2 months ago
- OpenExSys_CoherentCache a directory-based MESI protocol coherent cache IP.☆21Mar 25, 2025Updated 10 months ago
- Designing a Multi-Agent Fabric Integration Architecture to run on de10-lite FPGA.☆17Feb 2, 2026Updated 2 weeks ago
- UVM testbench for verifying the Pulpino SoC☆13Mar 23, 2020Updated 5 years ago
- ☆17Dec 21, 2020Updated 5 years ago
- Universal Asynchronous Receiver/Transmitter (UART) with FIFOs Soft IP☆15Feb 18, 2025Updated 11 months ago
- Open-source AI Accelerator Stack integrating compute, memory, and software — from RTL to PyTorch.☆24Updated this week
- ☆16May 13, 2025Updated 9 months ago
- Formal Verification of RISC V IM Processor☆10Mar 27, 2022Updated 3 years ago
- ☆10Dec 15, 2023Updated 2 years ago
- SystemVerilog implementation of the AHB to TileLink UL (Uncached Lightweight) bridge☆13Sep 9, 2022Updated 3 years ago
- Microarchitectural control flow integrity (𝜇CFI) verification checks whether there exists a control or data flow from instruction's ope…☆16Updated this week
- RISCV core RV32I/E.4 threads in a ring architecture☆33Jun 12, 2023Updated 2 years ago
- ☆29Oct 20, 2019Updated 6 years ago
- Gemini 30F2 (30F3 variant 00) MIPS Processor for NSCSCC2022☆11Sep 21, 2022Updated 3 years ago
- Latest in the line of the E32 processors with better/generic cache placement☆10Feb 25, 2023Updated 2 years ago
- vector multiplication adder accelerator (using chisel 3 and RocketChip RoCC ) 向量乘法累加加速器☆53Apr 6, 2020Updated 5 years ago
- General Purpose Graphics Processing Unit (GPGPU) IP Core☆11Jul 4, 2014Updated 11 years ago
- ☆21Sep 26, 2025Updated 4 months ago
- work in SSRL, SOC/NOC/Chiplet Design, DDR/UCIe/PCIe, UVM Framework☆38Nov 24, 2022Updated 3 years ago
- A configurable general purpose graphics processing unit for☆12May 18, 2019Updated 6 years ago
- GPU for OENG1167 in Verilog HDL for DE10 series boards☆15Nov 1, 2020Updated 5 years ago
- Provides automation scripts for building BFMs☆16Apr 19, 2025Updated 9 months ago
- DUTH RISC-V Superscalar Microprocessor☆33Oct 23, 2024Updated last year
- PCI Express controller model☆71Oct 5, 2022Updated 3 years ago
- SoC Based on ARM Cortex-M3☆37May 16, 2025Updated 9 months ago
- A 32-bit out-of-order RISC-V superscalar for Xilinx FPGAs.☆15Jan 14, 2022Updated 4 years ago
- ☆14Nov 5, 2017Updated 8 years ago
- APB Logic☆23Jan 22, 2026Updated 3 weeks ago
- Implementation of a binary search tree algorithm in a FPGA/ASIC IP☆21Sep 5, 2021Updated 4 years ago