sld-columbia / esp-cachesLinks
SystemVerilog overhaul of ESP L2 and LLC caches with directory based protocol
☆17Updated 8 months ago
Alternatives and similar repositories for esp-caches
Users that are interested in esp-caches are comparing it to the libraries listed below
Sorting:
- ☆30Updated 3 weeks ago
- verification of simple axi-based cache☆18Updated 6 years ago
- ☆19Updated last month
- The official NaplesPU hardware code repository☆19Updated 6 years ago
- ☆12Updated 6 months ago
- A DDR3 Controller that uses the Xilinx MIG-7 PHY to interface with DDR3 devices.☆11Updated 4 years ago
- ☆27Updated 6 years ago
- HW-SW Co-Simulation Library for AMBA AXI BFM using DPI/VPI☆36Updated 10 months ago
- DUTH RISC-V Superscalar Microprocessor☆31Updated last year
- ☆31Updated 5 years ago
- ☆13Updated 8 months ago
- Functional Verification the MMU (Memory Management Unit) of a multiprocessor with Data Cache and Instruction Cache☆13Updated 10 years ago
- ☆10Updated 3 years ago
- 128KB AXI cache (32-bit in, 256-bit out)☆54Updated 4 years ago
- HLS for Networks-on-Chip☆37Updated 4 years ago
- Binary Single Precision Floating-point Fused Multiply-Add Unit Design (Verilog HDL)☆22Updated 12 years ago
- Andes Vector Extension support added to riscv-dv☆17Updated 5 years ago
- Development of a Network on Chip Simulation using SystemC.☆33Updated 8 years ago
- CS533 Course Project (ongoing) - Exploring Parallel Architectures for Neural Processing Unit Implementations☆19Updated 8 years ago
- Skid Buffer and Pipeline Skid Buffer designed in Verilog/System Verilog.☆26Updated 2 weeks ago
- DUTH RISC-V Microprocessor☆22Updated 11 months ago
- Implementation of the pipelined RISC V processor with many useful features as fully bypassing, dynamic branch prediction, single and mult …☆16Updated last year
- CORE-V MCU UVM Environment and Test Bench☆24Updated last year
- AXI3 Bus Functional Models (Initiator & Target)☆29Updated 2 years ago
- ☆13Updated 2 years ago
- The PULP RI5CY core modified for Verilator modeling and as a GDB server.☆25Updated 6 years ago
- OpenExSys_CoherentCache a directory-based MESI protocol coherent cache IP.☆17Updated 7 months ago
- ☆15Updated 3 years ago
- CHIPKIT: An agile, reusable open-source framework for rapid test chip development☆42Updated 5 years ago
- IPs for data-plane integration of Hardware Processing Engines (HWPEs) within a PULP system☆20Updated last week