anan-cn / Open-Source-Network-on-Chip-Router-RTL
☆75Updated 10 years ago
Alternatives and similar repositories for Open-Source-Network-on-Chip-Router-RTL
Users that are interested in Open-Source-Network-on-Chip-Router-RTL are comparing it to the libraries listed below
Sorting:
- A verilog implementation for Network-on-Chip☆73Updated 7 years ago
- ☆33Updated 6 years ago
- RTL Network-on-Chip Router Design in SystemVerilog by Andrea Galimberti, Filippo Testa and Alberto Zeni☆126Updated 7 years ago
- HDL code for a DDR4 memory controller implementing an Open Page Policy and Out of Order execution.☆74Updated 7 years ago
- Prototype-network-on-chip (ProNoC) is an EDA tool that facilitates prototyping of custom heterogeneous NoC-based many-core-SoC (MCSoC).☆56Updated 2 months ago
- NoC (Network-on-Chip) generator that generates Verilog HDL model of NoC consisting of on-chip routers☆62Updated 5 years ago
- Xilinx AXI VIP example of use☆38Updated 4 years ago
- INT8 & FP16 multiplier accumulator (MAC) design with UVM verification completed.☆100Updated 4 years ago
- General Purpose AXI Direct Memory Access☆49Updated last year
- A generic implementation of AMBA AXI4 communication protocol. The design provides a master, a slave and an interconnect with multiple mas…☆38Updated 2 years ago
- 16-bit Adder Multiplier hardware on Digilent Basys 3☆74Updated last year
- An AXI4 crossbar implementation in SystemVerilog☆148Updated this week
- Source code of the paper "Low-Cost and Programmable CRC Implementation based on FPGA"☆42Updated 4 years ago
- eyeriss-chisel3☆40Updated 3 years ago
- round robin arbiter☆73Updated 10 years ago
- ☆51Updated 2 years ago
- FFT generator using Chisel☆59Updated 3 years ago
- AXI4 and AXI4-Lite interface definitions☆92Updated 4 years ago
- Pure digital components of a UCIe controller☆62Updated this week
- ☆64Updated 6 years ago
- AXI Interconnect☆49Updated 3 years ago
- RaveNoC is a configurable HDL NoC (Network-On-Chip) suitable for MPSoCs and different MP applications☆166Updated 5 months ago
- Network on Chip Implementation written in SytemVerilog☆174Updated 2 years ago
- TCAM (Ternary Content-Addressable Memory) in Verilog☆48Updated last year
- HLS for Networks-on-Chip☆34Updated 4 years ago
- Systolic matrix multiplication kernel implemented on Xilinx PYNQ FPGA board☆14Updated 4 years ago
- A Style Guide for the Chisel Hardware Construction Language☆107Updated 3 years ago
- Public release☆51Updated 5 years ago
- This repository has a list of collaterals needed for ICC2 workshop. It has a modified version of raven_soc which was taped-out by Efables…☆31Updated 4 years ago
- 32 - bit floating point Multiplier Accumulator Unit (MAC)☆30Updated 4 years ago