☆86Oct 25, 2014Updated 11 years ago
Alternatives and similar repositories for Open-Source-Network-on-Chip-Router-RTL
Users that are interested in Open-Source-Network-on-Chip-Router-RTL are comparing it to the libraries listed below. We may earn a commission when you buy through links labeled 'Ad' on this page.
Sorting:
- A verilog implementation for Network-on-Chip☆86Feb 3, 2018Updated 8 years ago
- LIS Network-on-Chip Implementation☆34Aug 29, 2016Updated 9 years ago
- Network on Chip Implementation written in SytemVerilog☆210Aug 27, 2022Updated 3 years ago
- This is the RTL implementation of Shenjing, a low power neuromorphic computing accelerator☆18Apr 12, 2020Updated 6 years ago
- RTL Network-on-Chip Router Design in SystemVerilog by Andrea Galimberti, Filippo Testa and Alberto Zeni☆155Mar 19, 2018Updated 8 years ago
- Managed Database hosting by DigitalOcean • AdPostgreSQL, MySQL, MongoDB, Kafka, Valkey, and OpenSearch available. Automatically scale up storage and focus on building your apps.
- OpenSoC Fabric - A Network-On-Chip Generator☆178Jun 18, 2020Updated 6 years ago
- NoC based MPSoC☆11Jul 17, 2014Updated 12 years ago
- Network on Chip for MPSoC☆29Updated this week
- ☆29Oct 20, 2019Updated 6 years ago
- NoC (Network-on-Chip) generator that generates Verilog HDL model of NoC consisting of on-chip routers☆77Dec 30, 2019Updated 6 years ago
- Network on chip based neural network accelerator☆11Mar 25, 2021Updated 5 years ago
- A short tutorial on Gem5 with focus on how to run and modify Garnet2.0☆17Apr 18, 2018Updated 8 years ago
- RaveNoC is a configurable HDL NoC (Network-On-Chip) suitable for MPSoCs and different MP applications☆196Nov 18, 2024Updated last year
- Network on Chip Simulator☆331Jun 9, 2026Updated 2 months ago
- Managed Kubernetes at scale on DigitalOcean • AdDigitalOcean Kubernetes includes the control plane, bandwidth allowance, container registry, automatic updates, and more for free.
- A Fast, Low-Overhead On-chip Network☆325Aug 3, 2026Updated last week
- contains TLM2 based interfaces for AXI, ACE, CHI and other standard protocols☆69Jul 20, 2026Updated 3 weeks ago
- Netrace: a network packet trace reader☆16Jun 16, 2014Updated 12 years ago
- Direct Access Memory for MPSoC☆13Updated this week
- (Verilog) A simple convolution layer implementation with systolic array structure☆14May 9, 2022Updated 4 years ago
- ☆36Jul 29, 2026Updated last week
- Fork of the gem5 simulator with Garnet2.0 and DSENT extensions☆13Jan 28, 2019Updated 7 years ago
- Synthetic Traffic Models Capturing a Full Range of Cache Coherent Behaviour☆15May 17, 2019Updated 7 years ago
- Azadi (Freedom) is a 32-bit RISC-V CPU based System on Chip.☆34Aug 28, 2023Updated 2 years ago
- 1-Click AI Models by DigitalOcean Gradient • AdDeploy popular AI models on DigitalOcean Gradient GPU virtual machines with just a single click. Zero configuration with optimized deployments.
- DUTH RISC-V Superscalar Microprocessor☆35Oct 23, 2024Updated last year
- AXI3 Bus Functional Models (Initiator & Target)☆29Dec 26, 2022Updated 3 years ago
- MathLib DAC 2023 version☆13Sep 11, 2023Updated 2 years ago
- ☆19Aug 27, 2022Updated 3 years ago
- Theia: ray graphic processing unit☆20Jul 17, 2014Updated 12 years ago
- Prototype-network-on-chip (ProNoC) is an EDA tool that facilitates prototyping of custom heterogeneous NoC-based many-core-SoC (MCSoC).☆67Jun 10, 2026Updated 2 months ago
- ☆43Apr 28, 2019Updated 7 years ago
- NOCulator is a network-on-chip simulator providing cycle-accurate performance models for a wide variety of networks (mesh, torus, ring, h…☆31Feb 6, 2023Updated 3 years ago
- TileLink Uncached Lightweight (TL-UL) implementation on Chisel.☆25Nov 21, 2020Updated 5 years ago
- Deploy to Railway using AI coding agents - Free Credits Offer • AdUse Claude Code, Codex, OpenCode, and more. Autonomous software development now has the infrastructure to match with Railway.
- Public release☆59Sep 3, 2019Updated 6 years ago
- ☆19Updated this week
- Virtio front-end and back-end bridge, implemented with FPGA.☆30Sep 16, 2020Updated 5 years ago
- ☆13May 5, 2023Updated 3 years ago
- A DDR3 Controller that uses the Xilinx MIG-7 PHY to interface with DDR3 devices.☆12Aug 22, 2021Updated 4 years ago
- EE577b-Course-Project☆19May 6, 2020Updated 6 years ago
- A simple, scalable, source-synchronous, all-digital DDR link☆39Updated this week