☆83Oct 25, 2014Updated 11 years ago
Alternatives and similar repositories for Open-Source-Network-on-Chip-Router-RTL
Users that are interested in Open-Source-Network-on-Chip-Router-RTL are comparing it to the libraries listed below
Sorting:
- A verilog implementation for Network-on-Chip☆81Feb 3, 2018Updated 8 years ago
- LIS Network-on-Chip Implementation☆34Aug 29, 2016Updated 9 years ago
- Network on Chip Implementation written in SytemVerilog☆197Aug 27, 2022Updated 3 years ago
- This is the RTL implementation of Shenjing, a low power neuromorphic computing accelerator☆17Apr 12, 2020Updated 5 years ago
- RTL Network-on-Chip Router Design in SystemVerilog by Andrea Galimberti, Filippo Testa and Alberto Zeni☆147Mar 19, 2018Updated 8 years ago
- OpenSoC Fabric - A Network-On-Chip Generator☆176Jun 18, 2020Updated 5 years ago
- NoC based MPSoC☆11Jul 17, 2014Updated 11 years ago
- Network on Chip for MPSoC☆28Feb 28, 2026Updated 2 weeks ago
- ☆29Oct 20, 2019Updated 6 years ago
- NoC (Network-on-Chip) generator that generates Verilog HDL model of NoC consisting of on-chip routers☆77Dec 30, 2019Updated 6 years ago
- Network on chip based neural network accelerator☆10Mar 25, 2021Updated 4 years ago
- Netrace: a network packet trace reader☆14Jun 16, 2014Updated 11 years ago
- A short tutorial on Gem5 with focus on how to run and modify Garnet2.0☆17Apr 18, 2018Updated 7 years ago
- Network on Chip Simulator☆306Oct 26, 2025Updated 4 months ago
- RaveNoC is a configurable HDL NoC (Network-On-Chip) suitable for MPSoCs and different MP applications☆190Nov 18, 2024Updated last year
- contains TLM2 based interfaces for AXI, ACE, CHI and other standard protocols☆63Mar 13, 2026Updated last week
- A Fast, Low-Overhead On-chip Network☆272Mar 13, 2026Updated last week
- The official NaplesPU hardware code repository☆22Jul 27, 2019Updated 6 years ago
- Direct Access Memory for MPSoC☆13Feb 28, 2026Updated 2 weeks ago
- (Verilog) A simple convolution layer implementation with systolic array structure☆13May 9, 2022Updated 3 years ago
- ☆34Feb 17, 2026Updated last month
- Azadi (Freedom) is a 32-bit RISC-V CPU based System on Chip.☆32Aug 28, 2023Updated 2 years ago
- DUTH RISC-V Superscalar Microprocessor☆34Oct 23, 2024Updated last year
- Fork of the gem5 simulator with Garnet2.0 and DSENT extensions☆12Jan 28, 2019Updated 7 years ago
- Synthetic Traffic Models Capturing a Full Range of Cache Coherent Behaviour☆14May 17, 2019Updated 6 years ago
- AXI3 Bus Functional Models (Initiator & Target)☆30Dec 26, 2022Updated 3 years ago
- ☆13May 5, 2023Updated 2 years ago
- Prototype-network-on-chip (ProNoC) is an EDA tool that facilitates prototyping of custom heterogeneous NoC-based many-core-SoC (MCSoC).☆63Dec 15, 2025Updated 3 months ago
- ☆19Aug 27, 2022Updated 3 years ago
- Theia: ray graphic processing unit☆20Jul 17, 2014Updated 11 years ago
- ☆41Apr 28, 2019Updated 6 years ago
- NOCulator is a network-on-chip simulator providing cycle-accurate performance models for a wide variety of networks (mesh, torus, ring, h…☆29Feb 6, 2023Updated 3 years ago
- Public release☆58Sep 3, 2019Updated 6 years ago
- TileLink Uncached Lightweight (TL-UL) implementation on Chisel.☆22Nov 21, 2020Updated 5 years ago
- OpenExSys_CoherentCache a directory-based MESI protocol coherent cache IP.☆22Mar 25, 2025Updated 11 months ago
- A simple, scalable, source-synchronous, all-digital DDR link☆36Mar 13, 2026Updated last week
- General Purpose AXI Direct Memory Access☆63May 12, 2024Updated last year
- ☆19Oct 7, 2025Updated 5 months ago
- Virtio front-end and back-end bridge, implemented with FPGA.☆28Sep 16, 2020Updated 5 years ago