Alternatives and similar repositories for Open-Source-Network-on-Chip-Router-RTL

Users that are interested in Open-Source-Network-on-Chip-Router-RTL are comparing it to the libraries listed below

• matutani / nocgen
  NoC (Network-on-Chip) generator that generates Verilog HDL model of NoC consisting of on-chip routers
  ☆76Updated 6 years ago
• bakhshalipour / NoC-Verilog
  A verilog implementation for Network-on-Chip
  ☆81Updated 8 years ago
• amonemi / ProNoC
  Prototype-network-on-chip (ProNoC) is an EDA tool that facilitates prototyping of custom heterogeneous NoC-based many-core-SoC (MCSoC).
  ☆62Updated last month
• kuladeepsaireddy / OpenNoc
  ☆40Updated 6 years ago
• agalimberti / NoCRouter
  RTL Network-on-Chip Router Design in SystemVerilog by Andrea Galimberti, Filippo Testa and Alberto Zeni
  ☆144Updated 7 years ago
• ananthbhat94 / DDR4MemoryController
  HDL code for a DDR4 memory controller implementing an Open Page Policy and Out of Order execution.
  ☆85Updated 7 years ago
• esynr3z / axi_vip_demo
  Xilinx AXI VIP example of use
  ☆43Updated 4 years ago
• dpretet / axi-crossbar
  An AXI4 crossbar implementation in SystemVerilog
  ☆208Updated 5 months ago
• taichi-ishitani / tnoc
  Network on Chip Implementation written in SytemVerilog
  ☆197Updated 3 years ago
• abdelrhman-oun / DDR5_PHY_WriteOperation
  ☆70Updated 3 years ago
• ic-lab-duth / NoCpad
  HLS for Networks-on-Chip
  ☆39Updated 4 years ago
• alexforencich / verilog-cam
  Verilog Content Addressable Memory Module
  ☆115Updated 3 years ago
• oprecomp / DDR4_controller
  ☆74Updated 5 years ago
• FPGA-Networking / Low-Cost-and-Programmable-CRC
  Source code of the paper "Low-Cost and Programmable CRC Implementation based on FPGA"
  ☆43Updated 5 years ago
• aignacio / axi_dma
  General Purpose AXI Direct Memory Access
  ☆62Updated last year
• suoglu / Fixed-Floating-Point-Adder-Multiplier
  16-bit Adder Multiplier hardware on Digilent Basys 3
  ☆83Updated 2 years ago
• ucb-bar / ucie
  An open-source UCIe implementation
  ☆82Updated last week
• aignacio / ravenoc
  RaveNoC is a configurable HDL NoC (Network-On-Chip) suitable for MPSoCs and different MP applications
  ☆187Updated last year
• freecores / round_robin_arbiter
  round robin arbiter
  ☆77Updated 11 years ago
• pulp-platform / fpu
  ☆58Updated 6 years ago
• hyoukjun / OpenSMART
  Public release
  ☆58Updated 6 years ago
• LCAI-TIHU / HW
  LCAI-TIHU HW is an AI inference processor which is comprised of RISC-V cpu, nvdla, NoC bus, PCIe module, DDR, SRAM, bootROM, DMA and peri…
  ☆44Updated 3 years ago
• ljgibbslf / basic_cache_core
  ☆31Updated 5 years ago
• bsc-loca / sauria
  SAURIA (Systolic-Array tensor Unit for aRtificial Intelligence Acceleration) is an open-source Convolutional Neural Network accelerator b…
  ☆82Updated 2 months ago
• pulp-platform / FlooNoC
  A Fast, Low-Overhead On-chip Network
  ☆265Updated last week
• mcjtag / tcam
  TCAM (Ternary Content-Addressable Memory) in Verilog
  ☆55Updated 2 years ago
• rgb000000 / eyeriss-chisel3
  eyeriss-chisel3
  ☆40Updated 3 years ago
• ic-lab-duth / RISC-V-Vector
  Vector processor for RISC-V vector ISA
  ☆136Updated 5 years ago
• tharunchitipolu / Dadda-Multiplier-using-CSA
  Dadda multiplier(8*8, 16*16, 32*32) in Verilog HDL.
  ☆39Updated last year
• hizbi-github / AXI4_Master_Interconnect_Slave
  A generic implementation of AMBA AXI4 communication protocol. The design provides a master, a slave and an interconnect with multiple mas…
  ☆43Updated 3 years ago