anan-cn / Open-Source-Network-on-Chip-Router-RTLLinks
☆78Updated 10 years ago
Alternatives and similar repositories for Open-Source-Network-on-Chip-Router-RTL
Users that are interested in Open-Source-Network-on-Chip-Router-RTL are comparing it to the libraries listed below
Sorting:
- NoC (Network-on-Chip) generator that generates Verilog HDL model of NoC consisting of on-chip routers☆67Updated 5 years ago
- RTL Network-on-Chip Router Design in SystemVerilog by Andrea Galimberti, Filippo Testa and Alberto Zeni☆129Updated 7 years ago
- A verilog implementation for Network-on-Chip☆77Updated 7 years ago
- Prototype-network-on-chip (ProNoC) is an EDA tool that facilitates prototyping of custom heterogeneous NoC-based many-core-SoC (MCSoC).☆59Updated last month
- ☆36Updated 6 years ago
- HDL code for a DDR4 memory controller implementing an Open Page Policy and Out of Order execution.☆79Updated 7 years ago
- 16-bit Adder Multiplier hardware on Digilent Basys 3☆81Updated 2 years ago
- HLS for Networks-on-Chip☆36Updated 4 years ago
- General Purpose AXI Direct Memory Access☆59Updated last year
- An AXI4 crossbar implementation in SystemVerilog☆175Updated last month
- Network on Chip Implementation written in SytemVerilog☆191Updated 3 years ago
- TCAM (Ternary Content-Addressable Memory) in Verilog☆53Updated last year
- Verilog Content Addressable Memory Module☆111Updated 3 years ago
- Public release☆56Updated 6 years ago
- Xilinx AXI VIP example of use☆42Updated 4 years ago
- ☆63Updated 3 years ago
- Pure digital components of a UCIe controller☆71Updated 3 weeks ago
- ☆66Updated 4 years ago
- Source code of the paper "Low-Cost and Programmable CRC Implementation based on FPGA"☆43Updated 4 years ago
- RaveNoC is a configurable HDL NoC (Network-On-Chip) suitable for MPSoCs and different MP applications☆176Updated 10 months ago
- SoC Based on ARM Cortex-M3☆33Updated 4 months ago
- Project repo for the POSH on-chip network generator☆50Updated 6 months ago
- ☆29Updated 5 years ago
- Advanced Architecture Labs with CVA6☆68Updated last year
- This tools offer many simulation of memory design detail parameter. Then you can setting these parameter to running result in your condit…☆18Updated 9 years ago
- round robin arbiter☆75Updated 11 years ago
- SAURIA (Systolic-Array tensor Unit for aRtificial Intelligence Acceleration) is an open-source Convolutional Neural Network accelerator b…☆58Updated last year
- Vector processor for RISC-V vector ISA☆128Updated 4 years ago
- BlackParrot on Zynq☆47Updated 6 months ago
- INT8 & FP16 multiplier accumulator (MAC) design with UVM verification completed.☆104Updated 5 years ago