Accelergy-Project / accelergy-timeloop-infrastructureLinks
Linux docker for the DNN accelerator exploration infrastructure composed of Accelergy and Timeloop
☆57Updated 5 months ago
Alternatives and similar repositories for accelergy-timeloop-infrastructure
Users that are interested in accelergy-timeloop-infrastructure are comparing it to the libraries listed below
Sorting:
- MICRO22 artifact evaluation for Sparseloop☆44Updated 3 years ago
- A Reconfigurable Accelerator with Data Reordering Support for Low-Cost On-Chip Dataflow Switching☆63Updated last week
- A scheduler for spatial DNN accelerators that generate high-performance schedules in one shot using mixed integer programming (MIP)☆83Updated 2 years ago
- MAERI: A DNN accelerator with reconfigurable interconnects to support flexible dataflow (http://synergy.ece.gatech.edu/tools/maeri/)☆66Updated 4 years ago
- Multi-core HW accelerator mapping optimization framework for layer-fused ML workloads.☆58Updated 2 months ago
- dMazeRunner: Dataflow acceleration optimization infrastructure for coarse-grained programmable accelerators☆47Updated 3 years ago
- RTL implementation of Flex-DPE.☆112Updated 5 years ago
- ☆40Updated last year
- ☆35Updated 5 years ago
- ☆71Updated 5 years ago
- FlexASR: A Reconfigurable Hardware Accelerator for Attention-based Seq-to-Seq Networks☆48Updated 7 months ago
- A systolic array simulator for multi-cycle MACs and varying-byte words, with the paper accepted to HPCA 2022.☆80Updated 3 years ago
- mNPUsim: A Cycle-accurate Multi-core NPU Simulator (IISWC 2023)☆64Updated 9 months ago
- Tool for optimize CNN blocking☆94Updated 5 years ago
- A reference implementation of the Mind Mappings Framework.☆30Updated 3 years ago
- ☆29Updated 3 years ago
- A framework for fast exploration of the depth-first scheduling space for DNN accelerators☆40Updated 2 years ago
- An FPGA accelerator for general-purpose Sparse-Matrix Dense-Matrix Multiplication (SpMM).☆84Updated last year
- High-Performance Sparse Linear Algebra on HBM-Equipped FPGAs Using HLS☆95Updated last year
- Exercises for exploring the Fibertree, Timeloop and Accelergy tools☆104Updated 5 months ago
- [ICASSP'20] DNN-Chip Predictor: An Analytical Performance Predictor for DNN Accelerators with Various Dataflows and Hardware Architecture…☆25Updated 3 years ago
- ☆33Updated 4 years ago
- An open-source parameterizable NPU generator with full-stack multi-target compilation stack for intelligent workloads.☆66Updated this week
- ☆72Updated 2 years ago
- ☆35Updated 6 months ago
- agile hardware-software co-design☆51Updated 3 years ago
- [TCAD'23] AccelTran: A Sparsity-Aware Accelerator for Transformers☆51Updated last year
- ☆28Updated 2 years ago
- Eyeriss chip simulator☆36Updated 5 years ago
- ☆48Updated 4 years ago