Accelergy-Project / accelergy-timeloop-infrastructure

Related projects ⓘ

Alternatives and complementary repositories for accelergy-timeloop-infrastructure

• Accelergy-Project / micro22-sparseloop-artifact
  MICRO22 artifact evaluation for Sparseloop
  ☆39Updated 2 years ago
• maeri-project / MAERI_bsv
  MAERI: A DNN accelerator with reconfigurable interconnects to support flexible dataflow (http://synergy.ece.gatech.edu/tools/maeri/)
  ☆59Updated 3 years ago
• kartik-hegde / mindmappings
  A reference implementation of the Mind Mappings Framework.
  ☆28Updated 2 years ago
• MPSLab-ASU / dMazeRunner
  dMazeRunner: Dataflow acceleration optimization infrastructure for coarse-grained programmable accelerators
  ☆44Updated 2 years ago
• maestro-project / confuciux
  ☆31Updated 3 years ago
• GATECH-EIC / AutoDNNchip
  ☆69Updated 4 years ago
• georgia-tech-synergy-lab / SIGMA
  RTL implementation of Flex-DPE.
  ☆91Updated 4 years ago
• maeri-project / FEATHER
  A Reconfigurable Accelerator with Data Reordering Support for Low-Cost On-Chip Dataflow Switching
  ☆30Updated last month
• he-actlab / planaria.code
  ☆25Updated 3 years ago
• KULeuven-MICAS / stream
  Multi-core HW accelerator mapping optimization framework for layer-fused ML workloads.
  ☆40Updated last week
• KULeuven-MICAS / DeFiNES
  A framework for fast exploration of the depth-first scheduling space for DNN accelerators
  ☆32Updated last year
• ucb-bar / cosa
  A scheduler for spatial DNN accelerators that generate high-performance schedules in one shot using mixed integer programming (MIP)
  ☆74Updated last year
• maestro-project / gamma
  ☆34Updated 4 months ago
• Accelergy-Project / processing-in-memory-design
  ☆24Updated 7 months ago
• hatsu3 / Sanger
  ☆41Updated 3 years ago
• diwu1990 / uSystolic-Sim
  A systolic array simulator for multi-cycle MACs and varying-byte words, with the paper accepted to HPCA 2022.
  ☆65Updated 3 years ago
• tissue3 / EyerissSimulator
  Eyeriss chip simulator
  ☆33Updated 4 years ago
• PSAL-POSTECH / ONNXim
  ONNXim is a fast cycle-level simulator that can model multi-core NPUs for DNN inference
  ☆67Updated last week
• casys-kaist / mNPUsim
  mNPUsim: A Cycle-accurate Multi-core NPU Simulator (IISWC 2023)
  ☆38Updated 6 months ago
• harvard-acc / FlexASR
  FlexASR: A Reconfigurable Hardware Accelerator for Attention-based Seq-to-Seq Networks
  ☆42Updated 2 years ago
• Accelergy-Project / accelergy
  Accelergy is an energy estimation infrastructure for accelerator energy estimations
  ☆126Updated 2 months ago
• UCLA-VAST / FlexCNN
  ☆70Updated last year
• xuanyoya / Interstellar-CNN-scheduler
  Tool for optimize CNN blocking
  ☆93Updated 4 years ago
• DNN-Accelerators / Open-Source-IPs
  ☆32Updated 5 years ago
• fffasttime / AnyPackingNet
  ☆24Updated 8 months ago
• sfu-arch / SpGEMM
  ☆33Updated 3 years ago
• cwfletcher / buffets
  Implementations of Buffets, which are efficient, composable idioms for implementing Explicit Decoupled Data Orchestration.
  ☆63Updated 5 years ago
• actlab-genesys / GeneSys
  An open-source parameterizable NPU generator with full-stack multi-target compilation stack for intelligent workloads.
  ☆31Updated 7 months ago
• Accelergy-Project / pytorch2timeloop-converter
  ☆10Updated last month
• diwu1990 / UnarySim
  This is a general-purpose simulator for unary computing based on PyTorch, with the paper accepted to ISCA 2020 and awarded IEEE Micro Top…
  ☆41Updated last year