kuladeepsaireddy / OpenNoc
☆31Updated 5 years ago
Alternatives and similar repositories for OpenNoc:
Users that are interested in OpenNoc are comparing it to the libraries listed below
- General Purpose AXI Direct Memory Access☆49Updated 10 months ago
- A verilog implementation for Network-on-Chip☆73Updated 7 years ago
- tpu-systolic-array-weight-stationary☆22Updated 3 years ago
- SystemVerilog files for lab project on a DNN hardware accelerator☆16Updated 3 years ago
- Prototype-network-on-chip (ProNoC) is an EDA tool that facilitates prototyping of custom heterogeneous NoC-based many-core-SoC (MCSoC).☆52Updated last week
- ☆26Updated 5 years ago
- 32 - bit floating point Multiplier Accumulator Unit (MAC)☆29Updated 4 years ago
- eyeriss-chisel3☆40Updated 2 years ago
- ☆43Updated 2 years ago
- The memory model was leveraged from micron.☆22Updated 6 years ago
- 128KB AXI cache (32-bit in, 256-bit out)☆48Updated 3 years ago
- ☆19Updated 2 years ago
- AXI Interconnect☆47Updated 3 years ago
- A generic implementation of AMBA AXI4 communication protocol. The design provides a master, a slave and an interconnect with multiple mas…☆34Updated 2 years ago
- INT8 & FP16 multiplier accumulator (MAC) design with UVM verification completed.☆93Updated 4 years ago
- ☆14Updated last year
- LCAI-TIHU HW is an AI inference processor which is comprised of RISC-V cpu, nvdla, NoC bus, PCIe module, DDR, SRAM, bootROM, DMA and peri…☆36Updated 2 years ago
- verification of simple axi-based cache☆18Updated 5 years ago
- Convolutional Neural Network Implemented in Verilog for System on Chip☆27Updated 5 years ago
- work in SSRL, SOC/NOC/Chiplet Design, DDR/UCIe/PCIe, UVM Framework☆30Updated 2 years ago
- AXI master to AHB slave, support INCR/WRAP, out of standing, do not advanced feature such as support out of order, retry, split, etc☆39Updated 3 years ago
- SoC Based on ARM Cortex-M3☆28Updated last week
- 16-bit Adder Multiplier hardware on Digilent Basys 3☆70Updated last year
- ☆71Updated 10 years ago
- Base on Synopsys platform using VCS,DC,ICC,PT.☆11Updated 3 years ago
- ☆63Updated 6 years ago
- This repository has a list of collaterals needed for ICC2 workshop. It has a modified version of raven_soc which was taped-out by Efables…☆30Updated 4 years ago
- Two Level Cache Controller implementation in Verilog HDL☆41Updated 4 years ago
- Systolic matrix multiplication kernel implemented on Xilinx PYNQ FPGA board☆13Updated 4 years ago