Alternatives and similar repositories for an-fpga-implementation-of-low-latency-noc-based-mpsoc:

Users that are interested in an-fpga-implementation-of-low-latency-noc-based-mpsoc are comparing it to the libraries listed below

• linkuri267 / cnn_accelerator
  CNN accelerator using NoC architecture
  ☆15Updated 6 years ago
• PacoReinaCampo / MPSoC-RISCV
  Multi-Processor System on Chip with RISCV-32 / RISCV-64 / RISCV-128
  ☆13Updated last month
• hyoukjun / microswitch-noc
  ☆24Updated 5 years ago
• loghall / axi_cache
  verification of simple axi-based cache
  ☆18Updated 5 years ago
• chad-q / andes-vector-riscv-dv
  Andes Vector Extension support added to riscv-dv
  ☆14Updated 4 years ago
• EngAhmed21 / RISC-V-Processor-with-Pipelining
  Implementation of the pipelined RISC V processor with many useful features as fully bypassing, dynamic branch prediction, single and mult…
  ☆14Updated last year
• GuiZhaoCodeSource / Func_Verif_MMU_Code_Source
  Functional Verification the MMU (Memory Management Unit) of a multiprocessor with Data Cache and Instruction Cache
  ☆12Updated 9 years ago
• freecores / wb_dma
  WISHBONE DMA/Bridge IP Core
  ☆18Updated 10 years ago
• srohit0 / CORDIC
  CORDIC VLSI-IP for deep learning activation functions
  ☆13Updated 5 years ago
• freecores / pipelined_fft_64
  Pipelined FFT/IFFT 64 points processor
  ☆12Updated 10 years ago
• JoseIuri / UVM_Python_UVMC
  This repository contains an example of the connection between an UVM Testbench and a Python reference model using UVM Connect from Mentor…
  ☆15Updated 5 years ago
• ljgibbslf / basic_cache_core
  ☆25Updated 4 years ago
• ShonTaware / LowPower
  Various low power labs using sky130
  ☆11Updated 3 years ago
• pulp-platform / hier-icache
  ☆11Updated 11 months ago
• iammituraj / skid_buffer
  Skid Buffer and Pipeline Skid Buffer designed in Verilog/System Verilog.
  ☆17Updated 6 months ago
• pulp-platform / axi2apb
  ☆18Updated 5 years ago
• pulp-platform / axi_llc
  ☆23Updated last month
• yayouz / CNN-accelerator
  DMA controller for CNN accelerator
  ☆13Updated 7 years ago
• Youssefmdany / Design-and-UVM-TB-of-RISC-V-Microprocessor
  Design and UVM-TB of RISC -V Microprocessor
  ☆14Updated 7 months ago
• rggen / rggen-sv-rtl
  Common SystemVerilog RTL modules for RgGen
  ☆12Updated last week
• TUM-LIS / lisnoc
  LIS Network-on-Chip Implementation
  ☆29Updated 8 years ago
• eanchlia / NN_Network_On_Chip
  Designed a pipelined calculation engine to read input/weights of neuron and compute/store results in SystemVerilog. Implemented fabric to…
  ☆12Updated 6 years ago
• StanfordAHA / AhaM3SoC
  SoC Based on ARM Cortex-M3
  ☆27Updated last month
• pulp-platform / apb
  APB Logic
  ☆14Updated 2 months ago
• frobino / Nostrum-SystemC-simulator
  SystemC simulator of a highly customizable Nostrum network-on-chip (NoC).
  ☆14Updated 10 years ago
• openhwgroup / core-v-mcu-uvm
  CORE-V MCU UVM Environment and Test Bench
  ☆18Updated 7 months ago
• jm2000 / RISCV-FPU
  Basic floating-point components for RISC-V processors
  ☆10Updated 7 years ago
• nullromo / compression-accelerator
  Implementation of the Snappy compression algorithm as a RoCC accelerator
  ☆11Updated 5 years ago
• pulp-platform / serial_link
  A simple, scalable, source-synchronous, all-digital DDR link
  ☆22Updated last week
• adki / cosim_bfm_library
  HW-SW Co-Simulation Library for AMBA AXI BFM using DPI/VPI
  ☆30Updated last month