msyksphinz-self / chisel-soc
☆9Updated 4 years ago
Alternatives and similar repositories for chisel-soc:
Users that are interested in chisel-soc are comparing it to the libraries listed below
- The RTL source for AnyCore RISC-V☆31Updated 3 years ago
- Implementation of Pythia: A Customizable Hardware Prefetching Framework Using Online Reinforcement Learning in Chisel HDL. To know more, …☆13Updated 3 years ago
- ☆24Updated last month
- ☆26Updated 5 years ago
- verification of simple axi-based cache☆18Updated 5 years ago
- Implementation of the Snappy compression algorithm as a RoCC accelerator☆11Updated 5 years ago
- YosysHQ SVA AXI Properties☆37Updated 2 years ago
- A barebones 64-bit RISC-V micro-controller class CPU, implementing the I(nteger), M(ul/div), C(ompressed) and K(ryptography) extensions.☆44Updated 3 years ago
- ☆26Updated 4 years ago
- ☆21Updated 5 years ago
- StateMover is a checkpoint-based debugging framework for FPGAs.☆19Updated 2 years ago
- Original test vector of RISC-V Vector Extension☆11Updated 4 years ago
- DUTH RISC-V Superscalar Microprocessor☆30Updated 5 months ago
- HW-SW Co-Simulation Library for AMBA AXI BFM using DPI/VPI☆31Updated 3 months ago
- Skid Buffer and Pipeline Skid Buffer designed in Verilog/System Verilog.☆18Updated 7 months ago
- An Open-Source SCAlable Interface for ISA Extensionsfor RISC-V Processors. New Version:☆14Updated last year
- ☆19Updated 5 years ago
- RISCV core RV32I/E.4 threads in a ring architecture☆32Updated last year
- Andes Vector Extension support added to riscv-dv☆14Updated 4 years ago
- The ParaNut Processor - Highly Parallel and More Than Just a CPU Core☆33Updated last year
- CV32E40P is an in-order 4-stage RISC-V RV32IMFCXpulp CPU based on RI5CY from PULP-Platform☆19Updated last month
- ☆16Updated 5 years ago
- Platform Level Interrupt Controller☆37Updated 10 months ago
- 128KB AXI cache (32-bit in, 256-bit out)☆48Updated 3 years ago
- Contains commonly used UVM components (agents, environments and tests).☆28Updated 6 years ago
- RISC-V soft-core PEs for TaPaSCo☆18Updated 9 months ago
- Advanced Architecture Labs with CVA6☆55Updated last year
- The memory model was leveraged from micron.☆22Updated 7 years ago
- RiftCore is a 9-stage, single-issue, out-of-order 64-bits RISC-V Core, which supports RV64IMC and 3-level Cache System☆38Updated 2 years ago
- ☆10Updated 2 years ago