UVM components for DSP tasks (MODulation/DEModulation)
☆16Mar 2, 2022Updated 4 years ago
Alternatives and similar repositories for uvm_modem
Users that are interested in uvm_modem are comparing it to the libraries listed below. We may earn a commission when you buy through links labeled 'Ad' on this page.
Sorting:
- Functional Verification the MMU (Memory Management Unit) of a multiprocessor with Data Cache and Instruction Cache☆14Nov 9, 2015Updated 10 years ago
- Support code for DVCon 2021 paper submission☆13Mar 1, 2021Updated 5 years ago
- A Xtext based SystemRDL editor with syntax highlighting and context sensitive help☆12Feb 9, 2024Updated 2 years ago
- Common Agent is a generic agent implemented in SystemVerilog, based on UVM methodology, which can be easily extended to create very fast …☆13Apr 29, 2015Updated 11 years ago
- make your verilog DUT test more smart☆22Sep 9, 2016Updated 9 years ago
- Virtual machines for every use case on DigitalOcean • AdGet dependable uptime with 99.99% SLA, simple security tools, and predictable monthly pricing with DigitalOcean's virtual machines, called Droplets.
- Multi-Processor System on Chip verified with UVM/OSVVM/FV☆37Aug 7, 2026Updated last week
- Universal Hardware Data Model. A complete modeling of the IEEE SystemVerilog Object Model with VPI Interface, Elaborator, Serialization, …☆19Jul 22, 2026Updated 3 weeks ago
- Functional Verification of Physical Layer of PCI Express Gen5.0 Graduation Project Using UVM☆34Jul 17, 2025Updated last year
- A CSV file parser, written in SystemVerilog☆27Jul 13, 2016Updated 10 years ago
- ☆16Jul 15, 2026Updated last month
- SystemVerilog RTL and UVM RAL model generators for RgGen☆17Jul 1, 2026Updated last month
- A UVM verification with a APB BFM (Bus functional model), connected to two write-only DAC and two read-only ADC slaves. The sequence gene…☆17Jul 7, 2018Updated 8 years ago
- Backup: Library implementing a C TLM-2 style to bridge C models to SystemC TLM-2.0 (C++) from GreenSocs (https://git.greensocs.com/tlm/tl…☆19Aug 13, 2018Updated 8 years ago
- PCIe System Verilog Verification Environment developed for PCIe course☆16Mar 26, 2024Updated 2 years ago
- Bare Metal GPUs on DigitalOcean Gradient AI • AdPurpose-built for serious AI teams training foundational models, running large-scale inference, and pushing the boundaries of what's possible.
- YAMM package repository☆34Mar 20, 2023Updated 3 years ago
- Verification environment for the OpenHW Group's CORE-V High Performance Data Cache controller.☆27Jan 6, 2026Updated 7 months ago
- EasierUVM from Doulos now written in Python for easier UVM with framework and template generator☆13Sep 28, 2022Updated 3 years ago
- Public repository for PySysC, (From SC Common Practices Subgroup)☆56Dec 26, 2023Updated 2 years ago
- UVM interactive debug library☆36Feb 28, 2026Updated 5 months ago
- A mock framework for use with SVUnit☆19Jun 27, 2023Updated 3 years ago
- ☆15Nov 11, 2015Updated 10 years ago
- Hardware Design, Exploration, and Code Generation for SoC Designers☆12Dec 15, 2019Updated 6 years ago
- UVM resource from github, run simulation use YASAsim flow☆33Apr 25, 2020Updated 6 years ago
- Managed hosting for WordPress and PHP on Cloudways • AdManaged hosting for WordPress, Magento, Laravel, or PHP apps, on multiple cloud providers. Deploy in minutes on Cloudways by DigitalOcean.
- Using Nim to interface with SystemVerilog test benches via DPI-C☆32May 15, 2025Updated last year
- SystemVerilog wrapper over the Verilog Programming Interface (VPI)☆12Jun 3, 2025Updated last year
- Code snippets from articles published on www.amiq.com/consulting/blog☆37Jun 14, 2024Updated 2 years ago
- Contains source code for sin/cos table verification using UVM☆23Mar 9, 2021Updated 5 years ago
- This repository is compilation of basics of System Verilog Assertions in context of formal verification☆25Mar 7, 2019Updated 7 years ago
- Useful UVM extensions☆28Jul 10, 2024Updated 2 years ago
- UVM clock agent which frequency, duty cycle can be configured, clock slow and gating function are also available☆10Aug 24, 2020Updated 5 years ago
- ☆28Aug 8, 2026Updated last week
- Neural Turing Machine for a Multi-Processor System on Chip verified with UVM/OSVVM/FV☆12Updated this week
- Managed Kubernetes at scale on DigitalOcean • AdDigitalOcean Kubernetes includes the control plane, bandwidth allowance, container registry, automatic updates, and more for free.
- CORE-V MCU UVM Environment and Test Bench☆27Jul 19, 2024Updated 2 years ago
- This repository contains an example of the connection between an UVM Testbench and a Python reference model.☆12Nov 6, 2019Updated 6 years ago
- 📊 Tools collection (NumPy + Matplotlib based) to do spectral analysis and calculate the key performance parameters of an ADC☆22Jun 26, 2023Updated 3 years ago
- ☆36May 21, 2026Updated 2 months ago
- Calling a python function from SV, then have this python function call SV tasks. Useful for coding register sequences in python☆12Sep 23, 2022Updated 3 years ago
- SoC based on RISC V ISA☆10Apr 22, 2022Updated 4 years ago
- Reflection API for SystemVerilog☆14Mar 30, 2026Updated 4 months ago