Superscalar Out-of-Order NPU Design on FPGA
☆14May 17, 2024Updated 2 years ago
Alternatives and similar repositories for Neural-Processing-Unit-on-FPGA
Users that are interested in Neural-Processing-Unit-on-FPGA are comparing it to the libraries listed below. We may earn a commission when you buy through links labeled 'Ad' on this page.
Sorting:
- CS533 Course Project (ongoing) - Exploring Parallel Architectures for Neural Processing Unit Implementations☆22May 4, 2017Updated 9 years ago
- A 2-Way Super-Scalar OoO RISC-V Core Based on Intel P6 Microarchitecture.☆17Sep 27, 2022Updated 3 years ago
- A tiniest ASIC GPU that can render only two texture mapped triangles☆28Jan 2, 2026Updated 4 months ago
- Tensor Processing Unit implementation in Verilog☆14Mar 18, 2025Updated last year
- Various low power labs using sky130☆13Sep 3, 2021Updated 4 years ago
- Deploy to Railway using AI coding agents - Free Credits Offer • AdUse Claude Code, Codex, OpenCode, and more. Autonomous software development now has the infrastructure to match with Railway.
- Theia: ray graphic processing unit☆20Jul 17, 2014Updated 11 years ago
- A small Neural Network Processor for Edge devices.☆19Nov 22, 2022Updated 3 years ago
- RTL code of some arbitration algorithm☆16Aug 25, 2019Updated 6 years ago
- ☆23Mar 27, 2026Updated last month
- Used FPGA board and System Verilog to design controller, DMA, pipelined SIMD processor, and GEMM accelerator☆12Aug 26, 2023Updated 2 years ago
- 🟣 Dependency Injection interview questions and answers to help you prepare for your next technical interview in 2026.☆13Jan 4, 2026Updated 4 months ago
- ☆15May 6, 2026Updated 2 weeks ago
- Matrix Multiply and Accumulate unit written in System Verilog☆13Feb 7, 2019Updated 7 years ago
- System Verilog based RTL design of DMA controller for 8086 microprocessor based systems.☆29Mar 30, 2020Updated 6 years ago
- Open source password manager - Proton Pass • AdSecurely store, share, and autofill your credentials with Proton Pass, the end-to-end encrypted password manager trusted by millions.
- This is the UVM environment for UART-APB IP core. This environment contains full UVM components. It is only used for studing and invetiga…☆26Mar 8, 2026Updated 2 months ago
- ☆29Oct 20, 2019Updated 6 years ago
- Open NPU is an open-source project dedicated to creating a flexible, extensible, and high-performance neural processing unit (NPU) archit…☆21Jun 20, 2024Updated last year
- Verilog HDL implementation of SDRAM controller and SDRAM model☆42Jun 19, 2024Updated last year
- A powerful desktop application that helps developers solve coding problems by analyzing screenshots of code and providing AI-powered solu…☆39Aug 3, 2025Updated 9 months ago
- DUTH RISC-V Superscalar Microprocessor☆35Oct 23, 2024Updated last year
- ☆253Apr 8, 2024Updated 2 years ago
- RL-Pruner: Structured Pruning Using Reinforcement Learning for CNN Compression and Acceleration☆27Jun 8, 2025Updated 11 months ago
- Design & Implementation of Multi Clock Domain System using Verilog HDL☆13Oct 4, 2023Updated 2 years ago
- 1-Click AI Models by DigitalOcean Gradient • AdDeploy popular AI models on DigitalOcean Gradient GPU virtual machines with just a single click. Zero configuration with optimized deployments.
- Implementation of Sobel Filter in Verilog☆27Mar 10, 2017Updated 9 years ago
- Deep Reinforcement Learning with CartPole in Pytorch☆16Jun 13, 2020Updated 5 years ago
- Getting started with Zephyr RTOS on BluePill STM32F103C8 board☆15Aug 24, 2023Updated 2 years ago
- Static timing analysis (STA) is a method of validating the timing performance of a design by checking all possible paths for timing viola…☆17Oct 4, 2022Updated 3 years ago
- Verilog projects for simulation and logic synthesis (Icarus Verilog, YOSYS)☆22Apr 28, 2021Updated 5 years ago
- Exemplos de projetos com FreeRTOS e ESP32☆23Jun 22, 2020Updated 5 years ago
- AI Chip project☆34Jul 14, 2021Updated 4 years ago
- 256-bit vector processor based on the RISC-V vector (V) extension☆33May 1, 2021Updated 5 years ago
- SAURIA (Systolic-Array tensor Unit for aRtificial Intelligence Acceleration) is an open-source Convolutional Neural Network accelerator b…☆94Nov 26, 2025Updated 5 months ago
- Deploy on Railway without the complexity - Free Credits Offer • AdConnect your repo and Railway handles the rest with instant previews. Quickly provision container image services, databases, and storage volumes.
- TPU SDK☆20Oct 27, 2023Updated 2 years ago
- MicroPython ESP8266/ESP32 driver for TTP229-BSF 16-key capacitive keypad in serial interface mode☆18Aug 4, 2021Updated 4 years ago
- Transactional Verilog design and Verilator Testbench for a RISC-V TensorCore Vector co-processor for reproducible linear algebra☆63Dec 19, 2021Updated 4 years ago
- ☆16Apr 8, 2023Updated 3 years ago
- Small-scale Tensor Processing Unit built on an FPGA☆227Aug 4, 2019Updated 6 years ago
- hardware design of universal NPU(CNN accelerator) for various convolution neural network☆172Mar 5, 2025Updated last year
- Convolutional Neural Network RTL-level Design☆83Oct 22, 2021Updated 4 years ago