YqGe585 / Neural-Processing-Unit-on-FPGALinks
Superscalar Out-of-Order NPU Design on FPGA
☆11Updated last year
Alternatives and similar repositories for Neural-Processing-Unit-on-FPGA
Users that are interested in Neural-Processing-Unit-on-FPGA are comparing it to the libraries listed below
Sorting:
- Implementation of the pipelined RISC V processor with many useful features as fully bypassing, dynamic branch prediction, single and mult…☆17Updated last year
- RTL code of some arbitration algorithm☆14Updated 6 years ago
- Design and UVM-TB of RISC -V Microprocessor☆30Updated last year
- Pipelined Processor which implements RV32i Instruction Set. Also contains pipelined L1 4-way set-associative Instruction Cache, direct-ma…☆14Updated 2 years ago
- CS533 Course Project (ongoing) - Exploring Parallel Architectures for Neural Processing Unit Implementations☆19Updated 8 years ago
- ☆20Updated 3 years ago
- uvm_axi4lite is a uvm package for modeling and verifying AXI4 Lite protocol☆29Updated 10 months ago
- UVM Testbench for synchronus fifo☆17Updated 5 years ago
- ☆14Updated 2 years ago
- - A 1X3 Router (capable of routing the data packets to three different clients form a single source network) was designed, including a re…☆11Updated 6 years ago
- Prototype-network-on-chip (ProNoC) is an EDA tool that facilitates prototyping of custom heterogeneous NoC-based many-core-SoC (MCSoC).☆59Updated last week
- SoC Based on ARM Cortex-M3☆34Updated 6 months ago
- A generic implementation of AMBA AXI4 communication protocol. The design provides a master, a slave and an interconnect with multiple mas…☆42Updated 3 years ago
- 128KB AXI cache (32-bit in, 256-bit out)☆55Updated 4 years ago
- AXI Interconnect☆54Updated 4 years ago
- The memory model was leveraged from micron.☆24Updated 7 years ago
- verification of the basic router protocol with UVM testbech //INCLUDED WITH RTL☆14Updated 6 years ago
- I present a novel pipelined fast Fourier transform (FFT) architecture which is capable of producing the output sequence in normal order. …☆48Updated 2 years ago
- work in SSRL, SOC/NOC/Chiplet Design, DDR/UCIe/PCIe, UVM Framework☆36Updated 3 years ago
- General Purpose AXI Direct Memory Access☆61Updated last year
- ☆10Updated 5 years ago
- ☆17Updated 10 years ago
- This is a Multi master Multi slave compatible system bus design modeled using verilog. This is much like AMBA AHB Specification☆32Updated 5 years ago
- Universal Asynchronous Receiver/Transmitter (UART) with FIFOs Soft IP☆14Updated 9 months ago
- Two Level Cache Controller implementation in Verilog HDL☆53Updated 5 years ago
- An 8 input interrupt controller written in Verilog.☆28Updated 13 years ago
- ☆15Updated 3 years ago
- ☆65Updated 3 years ago
- A Verilog implementation of a processor cache.☆34Updated 7 years ago
- ☆11Updated 3 years ago