A Direct Memory Access Controller (DMAC) with AHB-lite bus interface
☆17Oct 6, 2024Updated last year
Alternatives and similar repositories for MS_DMAC_AHBL
Users that are interested in MS_DMAC_AHBL are comparing it to the libraries listed below
Sorting:
- AHB/APB SRAM Inf, VCS&Verdi Sim.☆16Jun 20, 2022Updated 3 years ago
- MMC小组开发的一个基于Cortex-M0的ARM处理器核的无线SOC设计☆22May 24, 2023Updated 2 years ago
- Raptor is an SoC Design Template based on Arm Cortex M0 or M3 core.☆22Oct 9, 2019Updated 6 years ago
- ☆20Nov 18, 2022Updated 3 years ago
- ☆11Mar 10, 2023Updated 2 years ago
- Verilog code that does 2D Low Pass Filter on a greyscale image☆10Sep 22, 2015Updated 10 years ago
- A simple spidergon network-on-chip with wormhole switching feature☆12Mar 22, 2021Updated 4 years ago
- Verification IP for Watchdog☆12Apr 6, 2021Updated 4 years ago
- Universal Asynchronous Receiver/Transmitter (UART) with FIFOs Soft IP☆15Feb 18, 2025Updated last year
- Direct Access Memory for MPSoC☆13Updated this week
- An 8 input interrupt controller written in Verilog.☆28Mar 22, 2012Updated 13 years ago
- Designed a pipelined calculation engine to read input/weights of neuron and compute/store results in SystemVerilog. Implemented fabric to…☆12Feb 12, 2019Updated 7 years ago
- ☆21Sep 26, 2025Updated 5 months ago
- UVM Testbench for synchronus fifo☆19Aug 28, 2020Updated 5 years ago
- Various low power labs using sky130☆13Sep 3, 2021Updated 4 years ago
- practice configure AHB-Lite bus protocol☆19Mar 11, 2019Updated 6 years ago
- High Throughput Image Filters on FPGAs☆14Oct 17, 2017Updated 8 years ago
- ☆20Aug 22, 2022Updated 3 years ago
- SoC Based on ARM Cortex-M3☆37May 16, 2025Updated 9 months ago
- AHB-lite, AHB-APB bridge and extended APB side architecture in SystemVerilog☆17Sep 2, 2023Updated 2 years ago
- ☆18Apr 5, 2015Updated 10 years ago
- DSP WishBone Compatible Cores☆14Jul 17, 2014Updated 11 years ago
- ☆38Aug 12, 2015Updated 10 years ago
- ☆19Aug 11, 2022Updated 3 years ago
- ☆16Apr 21, 2019Updated 6 years ago
- this is an AHB to APB bridge with Synopsys VIP based test enviroment. RTL can be found from UVM website.☆20Jul 29, 2014Updated 11 years ago
- Attempt to setup a bridge between AHB and I2C by constructing dedicated modules of AHB master , AHB slave , APB master , APB slave, I2C m…☆22Feb 25, 2019Updated 7 years ago
- IC Verification & SV Demo☆58Sep 29, 2021Updated 4 years ago
- AXI4 with a FIFO integrated with VIP☆22Feb 29, 2024Updated 2 years ago
- soc integration script and integration smoke script☆24Sep 12, 2022Updated 3 years ago
- Ratatoskr NoC Simulator☆29Apr 13, 2021Updated 4 years ago
- A VerilogHDL MCU Core based ARMv6 Cortex-M0☆22Jan 31, 2020Updated 6 years ago
- Simple AMBA VIP, Include axi/ahb/apb☆31Jul 4, 2024Updated last year
- ☆29Oct 20, 2019Updated 6 years ago
- ☆35Mar 8, 2023Updated 2 years ago
- ☆31Aug 8, 2020Updated 5 years ago
- 【2022集创赛】Arm杯一等奖作品:Cortex-M0智能娱乐收音机 开源项目☆27Mar 21, 2023Updated 2 years ago
- PCIe System Verilog Verification Environment developed for PCIe course☆14Mar 26, 2024Updated last year
- Pipelined FFT/IFFT 256 points processor☆10Jul 17, 2014Updated 11 years ago