hkust-zhiyao / MasterRTL
MasterRTL: A Pre-Synthesis PPA Estimation Framework for Any RTL Design
☆42Updated 5 months ago
Alternatives and similar repositories for MasterRTL:
Users that are interested in MasterRTL are comparing it to the libraries listed below
- Generating Hardware Verification Assertions from Design Specifications via Multi-LLMs☆23Updated 4 months ago
- ☆22Updated 8 months ago
- Collection of digital hardware modules & projects (benchmarks)☆46Updated 3 months ago
- Annotating Slack Directly on Your Verilog: Fine-Grained RTL Timing Evaluation for Early Optimization☆22Updated 8 months ago
- This is a python repo for flattening Verilog☆16Updated 2 months ago
- ☆15Updated 2 years ago
- Gamora: Graph Learning based Symbolic Reasoning for Large-Scale Boolean Networks (DAC'23)☆49Updated 2 months ago
- DATE'24 paper: "Hierarchical Source-to-Post-Route QoR Prediction in High-Level Synthesis with GNNs"☆15Updated 3 months ago
- ☆25Updated 10 months ago
- ☆16Updated 3 years ago
- GPU-based logic synthesis tool☆81Updated 7 months ago
- PANDA: Architecture-Level Power Evaluation by Unifying Analytical and Machine Learning Solutions☆15Updated last year
- An open-source benchmark for generating design RTL with natural language☆95Updated 4 months ago
- Dataset for ML-guided Accelerator Design☆35Updated 3 months ago
- ☆28Updated 9 months ago
- A Logic Synthesis tool based on "Mockturtle: EPFL Logic Synthesis Library " and "ABC: System for Sequential Logic Synthesis and Formal Ve…☆25Updated this week
- The first version of TritonPart☆24Updated last year
- ☆28Updated last year
- An integrated CGRA design framework☆86Updated 4 months ago
- A collection of ISCAS,ITC,TAU and other Benchmark Circuits for EDA tool evaluation.☆43Updated 2 months ago
- The open-sourced version of BOOM-Explorer☆37Updated last year
- An Open-Source Analytical Placer for Large Scale Heterogeneous FPGAs using Deep-Learning Toolkit☆79Updated 2 months ago
- AutoCellLibX: Automated Standard Cell Library Extension Based on Pattern Mining☆12Updated 2 years ago
- Research paper based on or related to ABC.☆28Updated 2 weeks ago
- AMF-Placer 2.0: An open-source timing-driven analytical mixed-size FPGA placer of heterogeneous resources (LUT/FF/LUTRAM/MUX/CARRY/DSP/BR…☆99Updated last year
- High-Level Synthesis Performance Prediction using GNNs: Benchmarking, Modeling, and Advancing☆48Updated 9 months ago
- ☆38Updated 2 years ago
- A RISC-V BOOM Microarchitecture Power Modeling Framework☆24Updated last year
- ☆50Updated 5 months ago
- ☆14Updated last year