MasterRTL: A Pre-Synthesis PPA Estimation Framework for Any RTL Design
☆66May 29, 2025Updated 9 months ago
Alternatives and similar repositories for MasterRTL
Users that are interested in MasterRTL are comparing it to the libraries listed below
Sorting:
- Annotating Slack Directly on Your Verilog: Fine-Grained RTL Timing Evaluation for Early Optimization☆42May 29, 2025Updated 9 months ago
- A circuit-element level explainer to explain machine learning model's prediction on chip layouts.☆18Oct 30, 2023Updated 2 years ago
- PANDA: Architecture-Level Power Evaluation by Unifying Analytical and Machine Learning Solutions☆17Dec 18, 2023Updated 2 years ago
- CircuitFusion: Multimodal Circuit Representation Learning for Agile Chip Design (ICLR'25)☆33Apr 13, 2025Updated 10 months ago
- ☆18Feb 3, 2022Updated 4 years ago
- SpecLLM: Exploring Generation and Review of VLSI Design Specification with Large Language Model☆15Jan 29, 2024Updated 2 years ago
- ☆20Oct 27, 2022Updated 3 years ago
- Generating Hardware Verification Assertions from Design Specifications via Multi-LLMs☆50Oct 28, 2024Updated last year
- Problems and Results of IWLS 2023 Programming Contest☆16Apr 12, 2025Updated 10 months ago
- ☆19Dec 21, 2020Updated 5 years ago
- ☆13Jan 20, 2023Updated 3 years ago
- E-Syn: E-Graph Rewriting with Technology-Aware Cost Functions for Logic Synthesis (DAC 2024)☆41Jul 17, 2024Updated last year
- A new LLM solution for RTL code generation, achieving state-of-the-art performance in non-commercial solutions and outperforming GPT-3.5.☆255Feb 9, 2025Updated last year
- This is a repo to store circuit design datasets☆19Jan 17, 2024Updated 2 years ago
- NetTAG: A Multimodal RTL-and-Layout-Aligned Netlist Foundation Model via Text-Attributed Graph (DAC'25)☆24Dec 21, 2025Updated 2 months ago
- An open-source benchmark for generating design RTL with natural language☆162Nov 8, 2024Updated last year
- This is a python repo for flattening Verilog☆20Dec 19, 2025Updated 2 months ago
- DeepGate3 for ICCAD2024☆13May 26, 2025Updated 9 months ago
- [DATE 2022] PowerGear: Early-Stage Power Estimation in FPGA HLS via Heterogeneous Edge-Centric GNNs☆20Apr 15, 2022Updated 3 years ago
- Research paper based on or related to ABC.☆70Jan 19, 2026Updated last month
- ☆17Apr 16, 2024Updated last year
- ICCAD'23 Best Paper Award candidate: Robust GNN-based Representation Learning for HLS☆24May 23, 2024Updated last year
- GL0AM GPU Accelerated Gate Level Logic Simulator☆30Feb 11, 2026Updated 3 weeks ago
- GNN-RE datasets for circuit recognition☆56May 16, 2023Updated 2 years ago
- ☆27Jun 25, 2024Updated last year
- ☆45May 18, 2024Updated last year
- Gamora: Graph Learning based Symbolic Reasoning for Large-Scale Boolean Networks (DAC'23)☆58Jan 8, 2025Updated last year
- ☆30Apr 23, 2024Updated last year
- EPFL logic synthesis benchmarks☆231Nov 18, 2025Updated 3 months ago
- A RISC-V BOOM Microarchitecture Power Modeling Framework☆31May 12, 2023Updated 2 years ago
- LLM4HWDesign Starting Toolkit☆19Oct 4, 2024Updated last year
- ☆99Jun 24, 2025Updated 8 months ago
- GPU-based logic synthesis tool☆100Nov 27, 2025Updated 3 months ago
- Implementation of Pythia: A Customizable Hardware Prefetching Framework Using Online Reinforcement Learning in Chisel HDL. To know more, …☆17Oct 9, 2021Updated 4 years ago
- EPFL and ISCAS85 combinational benchmark circuits in generic gate verilog☆31Jan 17, 2020Updated 6 years ago
- Logic Synthesis System from UC Berkeley (Unofficial Distribution)☆15Jun 4, 2019Updated 6 years ago
- Problems and Results of IWLS 2022 Programming Contest☆22Apr 12, 2025Updated 10 months ago
- A collection of ISCAS,ITC,TAU and other Benchmark Circuits for EDA tool evaluation.☆67Jan 13, 2025Updated last year
- EDA wiki☆136Nov 3, 2025Updated 4 months ago