Alternatives and similar repositories for sns

Users that are interested in sns are comparing it to the libraries listed below

• hkust-zhiyao / MasterRTL
  MasterRTL: A Pre-Synthesis PPA Estimation Framework for Any RTL Design
  ☆66Updated 8 months ago
• ispras / hdl-benchmarks
  Collection of digital hardware modules & projects (benchmarks)
  ☆80Updated 2 months ago
• Yu-Maryland / Gamora
  Gamora: Graph Learning based Symbolic Reasoning for Large-Scale Boolean Networks (DAC'23)
  ☆56Updated last year
• cornell-zhang / HOGA
  Hop-Wise Graph Attention for Scalable and Generalizable Learning on Circuits
  ☆35Updated last year
• zshi0616 / python-deepgate
  ☆27Updated last year
• yaoxufeng / RTLRewriter-Bench
  ☆44Updated last year
• laiyao1 / ArithTreeRL
  The release for paper "Scalable and Effective Arithmetic Tree Generation for Adder and Multiplier Designs"
  ☆14Updated last year
• hkust-zhiyao / AssertLLM
  Generating Hardware Verification Assertions from Design Specifications via Multi-LLMs
  ☆50Updated last year
• amahzoon / genmul
  ☆19Updated 5 years ago
• cornell-zhang / eqmap
  Using e-graphs for logic synthesis (ICCAD'25)
  ☆32Updated this week
• Yu-Maryland / Verilog-to-PyG
  ☆30Updated last year
• HKUSTGZ-MICS-LYU / FlattenRTL
  This is a python repo for flattening Verilog
  ☆20Updated last month
• cure-lab / DeepGate2
  ☆16Updated 2 years ago
• HKUST-GZ-VLSI / Design-Dataset
  This is a repo to store circuit design datasets
  ☆19Updated 2 years ago
• TILOS-AI-Institute / MLCAD-2023-FPGA-Macro-Placement-Contest
  ☆31Updated 2 years ago
• JBlocklove / LLMs-for-EDA-Tutorial
  ☆59Updated 3 weeks ago
• SJTU-ECTL / ALSRAC
  ALSRAC: Approximate Logic Synthesis by Resubstitution with Approximate Care Set
  ☆21Updated last year
• scale-lab / BACS
  Benchmarks for Approximate Circuit Synthesis
  ☆17Updated 5 years ago
• cuhk-eda / CULS
  GPU-based logic synthesis tool
  ☆97Updated 2 months ago
• pku-dasys / easymac
  ☆18Updated 4 years ago
• hkust-zhiyao / RTL-Timer
  Annotating Slack Directly on Your Verilog: Fine-Grained RTL Timing Evaluation for Early Optimization
  ☆41Updated 8 months ago
• OSCC-Project / iMap
  Logic optimization and technology mapping tool.
  ☆20Updated 2 years ago
• hkust-zhiyao / CircuitFusion
  CircuitFusion: Multimodal Circuit Representation Learning for Agile Chip Design (ICLR'25)
  ☆33Updated 9 months ago
• SJTU-ECTL / GOMIL
  GOMIL: Global Optimization of Multiplier by Integer Linear Programming
  ☆13Updated 4 years ago
• UT-LCA / ML4Accel-Dataset
  Dataset for ML-guided Accelerator Design
  ☆43Updated last year
• zslwyuan / AMF-Placer
  AMF-Placer 2.0: An open-source timing-driven analytical mixed-size FPGA placer of heterogeneous resources (LUT/FF/LUTRAM/MUX/CARRY/DSP/BR…
  ☆109Updated last year
• krzhu / abcRL
  MLCAD 2020: Reinforcement for logic optimization sequence exploration
  ☆29Updated 5 years ago
• cure-lab / DeepGate
  This is an official implementation for "DeepGate: Learning Neural Representations of Logic Gates".
  ☆24Updated 2 years ago
• Yu-Maryland / MapTune
  MapTune: Advancing ASIC Technology Mapping via Reinforcement Learning Guided Library Tuning Mingju Liu, Daniel Robinson, Yingjie Li, Cunx…
  ☆22Updated 10 months ago
• Gy-Hu / E-Syn
  E-Syn: E-Graph Rewriting with Technology-Aware Cost Functions for Logic Synthesis (DAC 2024)
  ☆41Updated last year