Entropy-xcy / sns
☆15Updated 2 years ago
Alternatives and similar repositories for sns:
Users that are interested in sns are comparing it to the libraries listed below
- MasterRTL: A Pre-Synthesis PPA Estimation Framework for Any RTL Design☆43Updated 6 months ago
- ☆14Updated last year
- Gamora: Graph Learning based Symbolic Reasoning for Large-Scale Boolean Networks (DAC'23)☆49Updated 2 months ago
- ☆14Updated 6 years ago
- Generating Hardware Verification Assertions from Design Specifications via Multi-LLMs☆24Updated 4 months ago
- ☆16Updated 4 years ago
- MapTune: Advancing ASIC Technology Mapping via Reinforcement Learning Guided Library Tuning Mingju Liu, Daniel Robinson, Yingjie Li, Cunx…☆17Updated 5 months ago
- ☆25Updated 11 months ago
- ☆22Updated 8 months ago
- This is an official implementation for "DeepGate: Learning Neural Representations of Logic Gates".☆21Updated last year
- Collection of digital hardware modules & projects (benchmarks)☆49Updated 4 months ago
- ALSRAC: Approximate Logic Synthesis by Resubstitution with Approximate Care Set☆19Updated 3 months ago
- Annotating Slack Directly on Your Verilog: Fine-Grained RTL Timing Evaluation for Early Optimization☆22Updated 8 months ago
- E-Syn: E-Graph Rewriting with Technology-Aware Cost Functions for Logic Synthesis (DAC 2024)☆28Updated 8 months ago
- This is a python repo for flattening Verilog☆16Updated 2 months ago
- ☆28Updated last year
- Research paper based on or related to ABC.☆32Updated last week
- Logic optimization and technology mapping tool.☆18Updated last year
- Simple Python interface for ABC☆23Updated last year
- ☆11Updated 2 years ago
- Awesome machine learning for logic synthesis☆25Updated 2 years ago
- A Logic Synthesis tool based on "Mockturtle: EPFL Logic Synthesis Library " and "ABC: System for Sequential Logic Synthesis and Formal Ve…☆25Updated last week
- MLCAD 2020: Reinforcement for logic optimization sequence exploration☆28Updated 4 years ago
- This is a repo to store circuit design datasets☆15Updated last year
- LOSTIN: Logic Optimization via Spatio-Temporal Information with Hybrid Graph Models☆22Updated 2 years ago
- A collection of ISCAS,ITC,TAU and other Benchmark Circuits for EDA tool evaluation.☆43Updated 2 months ago
- GPU-based logic synthesis tool☆81Updated 8 months ago
- ☆50Updated 5 months ago
- Benchmarks for Approximate Circuit Synthesis☆15Updated 4 years ago
- ☆29Updated last year