Alternatives and similar repositories for tacas23-wasim

Users that are interested in tacas23-wasim are comparing it to the libraries listed below

• Gy-Hu / HWMCC24-benchmark
  Collection for submission (Hardware Model Checking Benchmark)
  ☆10Updated 7 months ago
• CoriolisSP / FuzzBtor2
  Random Generator of Btor2 Files
  ☆10Updated last year
• amahzoon / genmul
  ☆16Updated 4 years ago
• Gy-Hu / E-Syn
  E-Syn: E-Graph Rewriting with Technology-Aware Cost Functions for Logic Synthesis (DAC 2024)
  ☆32Updated 10 months ago
• NVlabs / FVEval
  LLM Evaluation Benchmark on Hardware Formal Verification
  ☆21Updated 2 months ago
• jix / kissat_extras
  A fork of the Kissat SAT solver with additional features. Supports incremental solving.
  ☆14Updated 2 years ago
• hkust-zhiyao / CircuitFusion
  CircuitFusion: Multimodal Circuit Representation Learning for Agile Chip Design (ICLR'25)
  ☆13Updated last month
• HybridCEC / Hybrid-CEC
  A high-efficiency hybrid solving CEC algorithm
  ☆11Updated 2 years ago
• ycunxi / ACEC_benchmarks
  Arithmetic multiplier benchmarks
  ☆11Updated 7 years ago
• NVlabs / GEM
  Open-source RTL logic simulator with CUDA acceleration
  ☆18Updated last week
• gipsyh / rIC3-HWMCC24
  rIC3 model checker for Hardware Model Checking Competition 2024(HWMCC'24) submission
  ☆11Updated 8 months ago
• Yu-Maryland / MapTune
  MapTune: Advancing ASIC Technology Mapping via Reinforcement Learning Guided Library Tuning Mingju Liu, Daniel Robinson, Yingjie Li, Cunx…
  ☆18Updated last month
• wjrforcyber / ABCPaperCheck
  Research paper based on or related to ABC.
  ☆43Updated last week
• amahzoon / RevSCA-2.0
  ☆10Updated 5 years ago
• d-kfmnn / amulet2
  AMulet 2. - A better AIG Multiplier Examination Tool
  ☆25Updated 2 years ago
• gpt4rtl / AutoSVA2
  ☆15Updated last year
• HKUSTGZ-MICS-LYU / FlattenRTL
  This is a python repo for flattening Verilog
  ☆16Updated 3 weeks ago
• IntelLabs / pycaliper
  PyCaliper is Python-based tooling infrastructure that allows the verification and synthesis of specifications (properties) for RTL (e.g.,…
  ☆22Updated 4 months ago
• HKUST-GZ-VLSI / Design-Dataset
  This is a repo to store circuit design datasets
  ☆17Updated last year
• makaimann / ride-core-demo
  A tutorial for setting up Symbolic Quick Error Detection (SQED) using the model checker, CoSA, on the Ride Core
  ☆12Updated 6 years ago
• OSCC-Project / iMap
  Logic optimization and technology mapping tool.
  ☆18Updated last year
• achieve-lab / assertion_data_for_LLM
  ☆15Updated 4 months ago
• upscale-project / generic-sqed-demo
  ☆13Updated 4 years ago
• yuzeng2333 / autoGenILA
  Automatic generation of architecture-level models for hardware from its RTL design.
  ☆14Updated 2 years ago
• Gy-Hu / AIG2INV
  DeepIC3: Guiding IC3 Algorithms by Graph Neural Network Clause Prediction (ASP-DAC 2024)
  ☆11Updated last year
• hkust-zhiyao / AssertLLM
  Generating Hardware Verification Assertions from Design Specifications via Multi-LLMs
  ☆30Updated 7 months ago
• gipsyh / rIC3
  Hardware Formal Verification Tool
  ☆52Updated this week
• SPbSAT / cirbo
  ☆21Updated this week
• SJTU-ECTL / GOMIL
  GOMIL: Global Optimization of Multiplier by Integer Linear Programming
  ☆13Updated 3 years ago
• ekiwi / open-source-formal-verification-for-chisel
  ☆11Updated 3 years ago