Alternatives and similar repositories for NetTAG

Users that are interested in NetTAG are comparing it to the libraries listed below

• hkust-zhiyao / AssertLLM
  Generating Hardware Verification Assertions from Design Specifications via Multi-LLMs
  ☆38Updated 11 months ago
• hkust-zhiyao / CircuitFusion
  CircuitFusion: Multimodal Circuit Representation Learning for Agile Chip Design (ICLR'25)
  ☆25Updated 5 months ago
• hkust-zhiyao / MasterRTL
  MasterRTL: A Pre-Synthesis PPA Estimation Framework for Any RTL Design
  ☆56Updated 4 months ago
• hkust-zhiyao / RTLLM
  An open-source benchmark for generating design RTL with natural language
  ☆133Updated 11 months ago
• HKUST-GZ-VLSI / Design-Dataset
  This is a repo to store circuit design datasets
  ☆18Updated last year
• HKUSTGZ-MICS-LYU / FlattenRTL
  This is a python repo for flattening Verilog
  ☆19Updated 4 months ago
• Entropy-xcy / sns
  ☆19Updated 2 years ago
• shailja-thakur / VGen
  ☆184Updated 11 months ago
• yaoxufeng / RTLRewriter-Bench
  ☆38Updated last year
• AutoBench / AutoBench
  ☆28Updated 5 months ago
• sjtu-zhao-lab / hierarchical-gnn-for-hls
  DATE'24 paper: "Hierarchical Source-to-Post-Route QoR Prediction in High-Level Synthesis with GNNs"
  ☆17Updated 9 months ago
• Yu-Maryland / Verilog-to-PyG
  ☆25Updated last year
• JBlocklove / LLMs-for-EDA-Tutorial
  ☆54Updated 4 months ago
• zshi0616 / python-deepgate
  ☆23Updated last year
• hkust-zhiyao / RTL-Coder
  A new LLM solution for RTL code generation, achieving state-of-the-art performance in non-commercial solutions and outperforming GPT-3.5.
  ☆227Updated 7 months ago
• laiyao1 / ArithTreeRL
  The release for paper "Scalable and Effective Arithmetic Tree Generation for Adder and Multiplier Designs"
  ☆14Updated last year
• aichipdesign / chipgptft
  Data is all you need: Finetuning LLMs for Chip Design via an Automated design-data augmentation framework (DAC 2024)
  ☆49Updated 9 months ago
• ekiwi / rtl-repair
  Fast Symbolic Repair of Hardware Design Code
  ☆26Updated 8 months ago
• NVlabs / FVEval
  LLM Evaluation Benchmark on Hardware Formal Verification
  ☆30Updated 6 months ago
• ispras / hdl-benchmarks
  Collection of digital hardware modules & projects (benchmarks)
  ☆62Updated 3 weeks ago
• OSCC-Project / iMap
  Logic optimization and technology mapping tool.
  ☆19Updated last year
• cornell-zhang / HOGA
  Hop-Wise Graph Attention for Scalable and Generalizable Learning on Circuits
  ☆32Updated last year
• amahzoon / genmul
  ☆18Updated 4 years ago
• PrincetonUniversity / AutoSVA
  AutoSVA is a tool to automatically generate formal testbenches for unit-level RTL verification. The goal is to, based on annotations made…
  ☆89Updated last year
• NVlabs / RTLFixer
  Fix syntax errors of LLM-generated RTL
  ☆37Updated last year
• GATECH-EIC / mg-verilog
  ☆48Updated last year
• ehw-fit / ariths-gen
  Generator of arithmetic circuits (multipliers, adders) and approximate circuits
  ☆36Updated last month
• NVlabs / verilog-eval
  Verilog evaluation benchmark for large language model
  ☆320Updated 2 months ago
• scale-lab / BACS
  Benchmarks for Approximate Circuit Synthesis
  ☆17Updated 5 years ago
• zlinaf / PowerGear
  [DATE 2022] PowerGear: Early-Stage Power Estimation in FPGA HLS via Heterogeneous Edge-Centric GNNs
  ☆18Updated 3 years ago