NetTAG: A Multimodal RTL-and-Layout-Aligned Netlist Foundation Model via Text-Attributed Graph (DAC'25)
☆25May 20, 2026Updated last month
Alternatives and similar repositories for NetTAG
Users that are interested in NetTAG are comparing it to the libraries listed below. We may earn a commission when you buy through links labeled 'Ad' on this page.
Sorting:
- CircuitFusion: Multimodal Circuit Representation Learning for Agile Chip Design (ICLR'25)☆41Apr 13, 2025Updated last year
- Generating Hardware Verification Assertions from Design Specifications via Multi-LLMs☆63Oct 28, 2024Updated last year
- A circuit-element level explainer to explain machine learning model's prediction on chip layouts.☆18Oct 30, 2023Updated 2 years ago
- This is a repo to store circuit design datasets☆19Jan 17, 2024Updated 2 years ago
- Annotating Slack Directly on Your Verilog: Fine-Grained RTL Timing Evaluation for Early Optimization☆43May 29, 2025Updated last year
- Deploy on Railway without the complexity - Free Credits Offer • AdConnect your repo and Railway handles the rest with instant previews. Quickly provision container image services, databases, and storage volumes.
- MasterRTL: A Pre-Synthesis PPA Estimation Framework for Any RTL Design☆72May 29, 2025Updated last year
- PANDA: Architecture-Level Power Evaluation by Unifying Analytical and Machine Learning Solutions☆19Dec 18, 2023Updated 2 years ago
- An open-source benchmark for generating design RTL with natural language☆202Nov 8, 2024Updated last year
- RISC-V Formal in Chisel☆13Apr 9, 2024Updated 2 years ago
- ☆23Mar 12, 2026Updated 3 months ago
- ☆13Jan 20, 2023Updated 3 years ago
- A Formal Verification Framework for Chisel☆20Apr 9, 2024Updated 2 years ago
- ☆18Nov 19, 2023Updated 2 years ago
- A new LLM solution for RTL code generation, achieving state-of-the-art performance in non-commercial solutions and outperforming GPT-3.5.☆304Feb 9, 2025Updated last year
- Virtual machines for every use case on DigitalOcean • AdGet dependable uptime with 99.99% SLA, simple security tools, and predictable monthly pricing with DigitalOcean's virtual machines, called Droplets.
- DATE'24 paper: "Hierarchical Source-to-Post-Route QoR Prediction in High-Level Synthesis with GNNs"☆21Dec 10, 2024Updated last year
- ☆18Jul 11, 2021Updated 4 years ago
- Logic optimization and technology mapping tool.☆20Oct 12, 2023Updated 2 years ago
- Generative Benchmark for LLM-Aided Hardware Design☆29Jun 4, 2025Updated last year
- Recent papers related to hardware formal verification.☆77Sep 20, 2023Updated 2 years ago
- ☆31Apr 23, 2024Updated 2 years ago
- LLM Evaluation Benchmark on Hardware Formal Verification☆44Apr 3, 2025Updated last year
- This repository contains all the parameters you need to synthesize the AlexNet by using Vivado High Level Synthesis.☆21Mar 5, 2018Updated 8 years ago
- ☆42Apr 11, 2025Updated last year
- Deploy on Railway without the complexity - Free Credits Offer • AdConnect your repo and Railway handles the rest with instant previews. Quickly provision container image services, databases, and storage volumes.
- PatchFuzz: Fuzzing for JavaScript Engine Incomplete Security Patches☆23Dec 17, 2025Updated 6 months ago
- Boosted E-Graph Extraction with Adaptive Heuristics and Exact Solving☆30Jan 7, 2026Updated 6 months ago
- Fuzz everything! Now let's fuzz chip!☆42Jun 5, 2026Updated last month
- Static timing analysis (STA) is a method of validating the timing performance of a design by checking all possible paths for timing viola…☆19Oct 4, 2022Updated 3 years ago
- LCAI-TIHU HW is an AI inference processor which is comprised of RISC-V cpu, nvdla, NoC bus, PCIe module, DDR, SRAM, bootROM, DMA and peri…☆46Jan 6, 2023Updated 3 years ago
- MAGE: A Multi-Agent Engine for Automated RTL Code Generation☆123Apr 11, 2025Updated last year
- ☆17Apr 16, 2024Updated 2 years ago
- Collection for submission (Hardware Model Checking Benchmark)☆13Nov 9, 2025Updated 7 months ago
- E-Syn: E-Graph Rewriting with Technology-Aware Cost Functions for Logic Synthesis (DAC 2024)☆44Jul 17, 2024Updated last year
- Deploy on Railway without the complexity - Free Credits Offer • AdConnect your repo and Railway handles the rest with instant previews. Quickly provision container image services, databases, and storage volumes.
- Formally proven secure design of the RISC-V core BOOM (Berkeley Out-of-Order Machine) w.r.t. transient execution attacks (e.g., Meltdown …☆15Jan 17, 2025Updated last year
- 🧠️🖥️2️⃣️0️⃣️0️⃣️1️⃣️🏠️ The source repository for the open source AI2001 Artificial Intelligence project.☆26Aug 8, 2025Updated 11 months ago
- ☆16May 2, 2026Updated 2 months ago
- Fuzzing for SpinalHDL☆17Oct 10, 2022Updated 3 years ago
- Re-host of ISCAS89 sequential benchmark circuits in higher level verilog (without "DFF")☆17Dec 3, 2021Updated 4 years ago
- A comprehensive, modular learning path for mastering UVM (Universal Verification Methodology) and pyuvm (Python UVM implementation) with …☆37May 30, 2026Updated last month
- PANDA: Architecture-Level Power Evaluation by Unifying Analytical and Machine Learning Solutions☆11Dec 18, 2023Updated 2 years ago