This is a python repo for flattening Verilog
☆20Dec 19, 2025Updated 6 months ago
Alternatives and similar repositories for FlattenRTL
Users that are interested in FlattenRTL are comparing it to the libraries listed below. We may earn a commission when you buy through links labeled 'Ad' on this page.
Sorting:
- ☆13Jan 20, 2023Updated 3 years ago
- Collection for submission (Hardware Model Checking Benchmark)☆13Nov 9, 2025Updated 7 months ago
- This is a repo to store circuit design datasets☆19Jan 17, 2024Updated 2 years ago
- Annotating Slack Directly on Your Verilog: Fine-Grained RTL Timing Evaluation for Early Optimization☆43May 29, 2025Updated last year
- QuteRTL: A RTL Front-End Towards Intelligent Synthesis and Verification☆18Nov 8, 2016Updated 9 years ago
- Virtual machines for every use case on DigitalOcean • AdGet dependable uptime with 99.99% SLA, simple security tools, and predictable monthly pricing with DigitalOcean's virtual machines, called Droplets.
- CircuitFusion: Multimodal Circuit Representation Learning for Agile Chip Design (ICLR'25)☆41Apr 13, 2025Updated last year
- MapTune: Advancing ASIC Technology Mapping via Reinforcement Learning Guided Library Tuning Mingju Liu, Daniel Robinson, Yingjie Li, Cunx…☆29Apr 9, 2025Updated last year
- Boosted E-Graph Extraction with Adaptive Heuristics and Exact Solving☆30Jan 7, 2026Updated 6 months ago
- ☆25Jun 23, 2024Updated 2 years ago
- Research paper based on or related to ABC.☆72Jun 11, 2026Updated 3 weeks ago
- ☆13Dec 31, 2022Updated 3 years ago
- A SystemVerilog Assertion dataset to improve hardware verification with LLMs.☆26Jun 9, 2025Updated last year
- ☆29Jun 25, 2024Updated 2 years ago
- ☆17Apr 16, 2024Updated 2 years ago
- Proton VPN Special Offer - Get 70% off • AdSpecial partner offer. Trusted by over 100 million users worldwide. Tested, Approved and Recommended by Experts.
- Logic Synthesis System from UC Berkeley (Unofficial Distribution)☆15Jun 4, 2019Updated 7 years ago
- E-Syn: E-Graph Rewriting with Technology-Aware Cost Functions for Logic Synthesis (DAC 2024)☆44Jul 17, 2024Updated last year
- A word hashing method based on vectors of letter n-grams. Currently transforms text into sequences of numbers.☆10Feb 27, 2018Updated 8 years ago
- Equivalence checking with Yosys☆60Jun 4, 2026Updated last month
- MasterRTL: A Pre-Synthesis PPA Estimation Framework for Any RTL Design☆72May 29, 2025Updated last year
- The official implementation of DeepRTL: Bridging Verilog Understanding and Generation with a Unified Representation Model (ICLR 2025)☆18Dec 18, 2025Updated 6 months ago
- GPU-based logic synthesis tool☆107Mar 31, 2026Updated 3 months ago
- ChatEDA: A Large Language Model Powered Autonomous Agent for EDA (TCAD'24, NAACL'25)☆55May 21, 2025Updated last year
- The open-sourced version of BOOM-Explorer☆51May 31, 2023Updated 3 years ago
- Deploy on Railway without the complexity - Free Credits Offer • AdConnect your repo and Railway handles the rest with instant previews. Quickly provision container image services, databases, and storage volumes.
- ☆59Jul 1, 2024Updated 2 years ago
- ☆21Nov 18, 2022Updated 3 years ago
- Random Generator of Btor2 Files☆10Sep 2, 2023Updated 2 years ago
- [IJCAI 2024] QiMeng-CPU-v1: Automated CPU Design by Learning from Input-Output Examples☆32May 4, 2025Updated last year
- An open-source benchmark for generating design RTL with natural language☆202Nov 8, 2024Updated last year
- 香山微架构开放验证第一期：昆明湖BPU模块UT测试模块及环境☆31Oct 20, 2024Updated last year
- Recent papers related to hardware formal verification.☆77Sep 20, 2023Updated 2 years ago
- LOSTIN: Logic Optimization via Spatio-Temporal Information with Hybrid Graph Models☆26May 29, 2022Updated 4 years ago
- Datasets for EDA LLM research☆46Jan 17, 2025Updated last year
- Deploy on Railway without the complexity - Free Credits Offer • AdConnect your repo and Railway handles the rest with instant previews. Quickly provision container image services, databases, and storage volumes.
- DeepIC3: Guiding IC3 Algorithms by Graph Neural Network Clause Prediction (ASP-DAC 2024)☆13Nov 2, 2023Updated 2 years ago
- OriGen: Enhancing RTL Code Generation with Code-to-Code Augmentation and Self-Reflection(ICCAD 2024)☆32Oct 20, 2024Updated last year
- ☆60Jan 19, 2026Updated 5 months ago
- Implementation of Pythia: A Customizable Hardware Prefetching Framework Using Online Reinforcement Learning in Chisel HDL. To know more, …☆17Oct 9, 2021Updated 4 years ago
- ☆10Nov 12, 2019Updated 6 years ago
- AutoSVA is a tool to automatically generate formal testbenches for unit-level RTL verification. The goal is to, based on annotations made…☆103Mar 29, 2024Updated 2 years ago
- Open-source RTL logic simulator with CUDA acceleration☆284Sep 30, 2025Updated 9 months ago