Alternatives and similar repositories for FlattenRTL

Users that are interested in FlattenRTL are comparing it to the libraries listed below

• hkust-zhiyao / MasterRTL
  MasterRTL: A Pre-Synthesis PPA Estimation Framework for Any RTL Design
  ☆55Updated 4 months ago
• HKUST-GZ-VLSI / Design-Dataset
  This is a repo to store circuit design datasets
  ☆18Updated last year
• hkust-zhiyao / AssertLLM
  Generating Hardware Verification Assertions from Design Specifications via Multi-LLMs
  ☆38Updated 11 months ago
• ispras / hdl-benchmarks
  Collection of digital hardware modules & projects (benchmarks)
  ☆62Updated 3 weeks ago
• Entropy-xcy / sns
  ☆19Updated 2 years ago
• yaoxufeng / RTLRewriter-Bench
  ☆38Updated last year
• PrincetonUniversity / AutoSVA
  AutoSVA is a tool to automatically generate formal testbenches for unit-level RTL verification. The goal is to, based on annotations made…
  ☆89Updated last year
• zshi0616 / python-deepgate
  ☆23Updated last year
• Yu-Maryland / Verilog-to-PyG
  ☆25Updated last year
• JBlocklove / LLMs-for-EDA-Tutorial
  ☆54Updated 4 months ago
• pku-dasys / easymac
  ☆16Updated 3 years ago
• amahzoon / genmul
  ☆17Updated 4 years ago
• ekiwi / rtl-repair
  Fast Symbolic Repair of Hardware Design Code
  ☆26Updated 8 months ago
• ehw-fit / ariths-gen
  Generator of arithmetic circuits (multipliers, adders) and approximate circuits
  ☆36Updated last month
• scale-lab / BACS
  Benchmarks for Approximate Circuit Synthesis
  ☆17Updated 5 years ago
• UT-LCA / ML4Accel-Dataset
  Dataset for ML-guided Accelerator Design
  ☆38Updated 10 months ago
• rachelselinar / DREAMPlaceFPGA
  An Open-Source Analytical Placer for Large Scale Heterogeneous FPGAs using Deep-Learning Toolkit
  ☆84Updated 5 months ago
• hkust-zhiyao / RTL-Timer
  Annotating Slack Directly on Your Verilog: Fine-Grained RTL Timing Evaluation for Early Optimization
  ☆32Updated 4 months ago
• Yu-Maryland / Gamora
  Gamora: Graph Learning based Symbolic Reasoning for Large-Scale Boolean Networks (DAC'23)
  ☆50Updated 8 months ago
• cuhk-eda / CULS
  GPU-based logic synthesis tool
  ☆90Updated last month
• cornell-zhang / HOGA
  Hop-Wise Graph Attention for Scalable and Generalizable Learning on Circuits
  ☆32Updated last year
• pku-dasys / cocoon
  An infrastructure for integrated EDA
  ☆41Updated 2 years ago
• zslwyuan / AMF-Placer
  AMF-Placer 2.0: An open-source timing-driven analytical mixed-size FPGA placer of heterogeneous resources (LUT/FF/LUTRAM/MUX/CARRY/DSP/BR…
  ☆105Updated last year
• zslwyuan / Light-HLS
  Fast, Accurate and Convenient Light-Weight HLS Framework for Academic Design Space Exploration and Evaluation. (LLVM-11)
  ☆61Updated 3 years ago
• IntelLabs / FloorSet
  ☆77Updated 3 months ago
• hkust-zhiyao / RTLLM
  An open-source benchmark for generating design RTL with natural language
  ☆133Updated 10 months ago
• baichen318 / boom-explorer-public
  The open-sourced version of BOOM-Explorer
  ☆43Updated 2 years ago
• jpsety / verilog_benchmark_circuits
  EPFL and ISCAS85 combinational benchmark circuits in generic gate verilog
  ☆28Updated 5 years ago
• OSCC-Project / iMap
  Logic optimization and technology mapping tool.
  ☆19Updated last year
• pku-dasys / pillars
  An integrated CGRA design framework
  ☆91Updated 6 months ago