This is a python repo for flattening Verilog
☆20Dec 19, 2025Updated 4 months ago
Alternatives and similar repositories for FlattenRTL
Users that are interested in FlattenRTL are comparing it to the libraries listed below. We may earn a commission when you buy through links labeled 'Ad' on this page.
Sorting:
- ☆13Jan 20, 2023Updated 3 years ago
- Collection for submission (Hardware Model Checking Benchmark)☆13Nov 9, 2025Updated 5 months ago
- This is a repo to store circuit design datasets☆19Jan 17, 2024Updated 2 years ago
- Annotating Slack Directly on Your Verilog: Fine-Grained RTL Timing Evaluation for Early Optimization☆44May 29, 2025Updated 10 months ago
- QuteRTL: A RTL Front-End Towards Intelligent Synthesis and Verification☆16Nov 8, 2016Updated 9 years ago
- Deploy open-source AI quickly and easily - Bonus Offer • AdRunpod Hub is built for open source. One-click deployment and autoscaling endpoints without provisioning your own infrastructure.
- CircuitFusion: Multimodal Circuit Representation Learning for Agile Chip Design (ICLR'25)☆36Apr 13, 2025Updated last year
- MapTune: Advancing ASIC Technology Mapping via Reinforcement Learning Guided Library Tuning Mingju Liu, Daniel Robinson, Yingjie Li, Cunx…☆26Apr 9, 2025Updated last year
- Boosted E-Graph Extraction with Adaptive Heuristics and Exact Solving☆30Jan 7, 2026Updated 3 months ago
- ☆24Jun 23, 2024Updated last year
- Research paper based on or related to ABC.☆72Jan 19, 2026Updated 2 months ago
- ☆13Dec 31, 2022Updated 3 years ago
- A SystemVerilog Assertion dataset to improve hardware verification with LLMs.☆25Jun 9, 2025Updated 10 months ago
- ☆28Jun 25, 2024Updated last year
- ☆17Apr 16, 2024Updated 2 years ago
- 1-Click AI Models by DigitalOcean Gradient • AdDeploy popular AI models on DigitalOcean Gradient GPU virtual machines with just a single click. Zero configuration with optimized deployments.
- Logic Synthesis System from UC Berkeley (Unofficial Distribution)☆15Jun 4, 2019Updated 6 years ago
- E-Syn: E-Graph Rewriting with Technology-Aware Cost Functions for Logic Synthesis (DAC 2024)☆42Jul 17, 2024Updated last year
- A word hashing method based on vectors of letter n-grams. Currently transforms text into sequences of numbers.☆10Feb 27, 2018Updated 8 years ago
- Equivalence checking with Yosys☆59Apr 9, 2026Updated last week
- MasterRTL: A Pre-Synthesis PPA Estimation Framework for Any RTL Design☆71May 29, 2025Updated 10 months ago
- The official implementation of DeepRTL: Bridging Verilog Understanding and Generation with a Unified Representation Model (ICLR 2025)☆16Dec 18, 2025Updated 4 months ago
- GPU-based logic synthesis tool☆101Mar 31, 2026Updated 2 weeks ago
- ChatEDA: A Large Language Model Powered Autonomous Agent for EDA (TCAD'24, NAACL'25)☆49May 21, 2025Updated 10 months ago
- The open-sourced version of BOOM-Explorer☆50May 31, 2023Updated 2 years ago
- Managed hosting for WordPress and PHP on Cloudways • AdManaged hosting for WordPress, Magento, Laravel, or PHP apps, on multiple cloud providers. Deploy in minutes on Cloudways by DigitalOcean.
- ☆57Jul 1, 2024Updated last year
- ☆21Nov 18, 2022Updated 3 years ago
- [IJCAI 2024] QiMeng-CPU-v1: Automated CPU Design by Learning from Input-Output Examples☆28May 4, 2025Updated 11 months ago
- Random Generator of Btor2 Files☆10Sep 2, 2023Updated 2 years ago
- An open-source benchmark for generating design RTL with natural language☆183Nov 8, 2024Updated last year
- 香山微架构开放验证第一期:昆明湖BPU模块UT测试模块及环境☆30Oct 20, 2024Updated last year
- Recent papers related to hardware formal verification.☆76Sep 20, 2023Updated 2 years ago
- LOSTIN: Logic Optimization via Spatio-Temporal Information with Hybrid Graph Models☆26May 29, 2022Updated 3 years ago
- Datasets for EDA LLM research☆42Jan 17, 2025Updated last year
- GPU virtual machines on DigitalOcean Gradient AI • AdGet to production fast with high-performance AMD and NVIDIA GPUs you can spin up in seconds. The definition of operational simplicity.
- ☆59Jan 19, 2026Updated 2 months ago
- DeepIC3: Guiding IC3 Algorithms by Graph Neural Network Clause Prediction (ASP-DAC 2024)☆13Nov 2, 2023Updated 2 years ago
- Implementation of Pythia: A Customizable Hardware Prefetching Framework Using Online Reinforcement Learning in Chisel HDL. To know more, …☆17Oct 9, 2021Updated 4 years ago
- AutoSVA is a tool to automatically generate formal testbenches for unit-level RTL verification. The goal is to, based on annotations made…☆101Mar 29, 2024Updated 2 years ago
- Open-source RTL logic simulator with CUDA acceleration☆267Sep 30, 2025Updated 6 months ago
- ELVE : ELVE Logic Visualization Engine☆11Jul 2, 2017Updated 8 years ago
- A switch joycon stick manager app for android☆16Dec 4, 2023Updated 2 years ago