Alternatives and similar repositories for python-deepgate

Users that are interested in python-deepgate are comparing it to the libraries listed below

• hkust-zhiyao / MasterRTL
  MasterRTL: A Pre-Synthesis PPA Estimation Framework for Any RTL Design
  ☆59Updated 6 months ago
• ispras / hdl-benchmarks
  Collection of digital hardware modules & projects (benchmarks)
  ☆74Updated 3 weeks ago
• zshi0616 / DeepGate2
  ☆31Updated 2 years ago
• panhomyoung / phyLS
  A Logic Synthesis tool based on "Mockturtle: EPFL Logic Synthesis Library " and "ABC: System for Sequential Logic Synthesis and Formal Ve…
  ☆39Updated this week
• hkustgz-zhang-lab / ABCPaperCheck
  Research paper based on or related to ABC.
  ☆63Updated last month
• santoshsmalagi / Benchmarks
  A collection of ISCAS,ITC,TAU and other Benchmark Circuits for EDA tool evaluation.
  ☆60Updated 11 months ago
• OSCC-Project / iMap
  Logic optimization and technology mapping tool.
  ☆20Updated 2 years ago
• Yu-Maryland / Gamora
  Gamora: Graph Learning based Symbolic Reasoning for Large-Scale Boolean Networks (DAC'23)
  ☆55Updated 11 months ago
• cuhk-eda / CULS
  GPU-based logic synthesis tool
  ☆97Updated last month
• HKUSTGZ-MICS-LYU / FlattenRTL
  This is a python repo for flattening Verilog
  ☆20Updated last week
• ABKGroup / TritonPart
  The first version of TritonPart
  ☆31Updated last year
• Entropy-xcy / sns
  ☆20Updated 3 years ago
• lamda-bbo / Open3DBench
  Official implementation of paper "Open3DBench: Open-Source Benchmark for 3D-IC Backend Implementation and PPA Evaluation".
  ☆75Updated 6 months ago
• yaoxufeng / RTLRewriter-Bench
  ☆42Updated last year
• Yu-Maryland / Verilog-to-PyG
  ☆29Updated last year
• hkust-zhiyao / AssertLLM
  Generating Hardware Verification Assertions from Design Specifications via Multi-LLMs
  ☆44Updated last year
• daeyeon22 / artificial_netlist_generator
  Artificial Netlist Generator
  ☆46Updated last year
• hkust-zhiyao / RTL-Timer
  Annotating Slack Directly on Your Verilog: Fine-Grained RTL Timing Evaluation for Early Optimization
  ☆37Updated 6 months ago
• zslwyuan / AMF-Placer
  AMF-Placer 2.0: An open-source timing-driven analytical mixed-size FPGA placer of heterogeneous resources (LUT/FF/LUTRAM/MUX/CARRY/DSP/BR…
  ☆109Updated last year
• NVlabs / INSTA
  ☆90Updated 6 months ago
• SJTU-ECTL / ALSRAC
  ALSRAC: Approximate Logic Synthesis by Resubstitution with Approximate Care Set
  ☆21Updated last year
• zslwyuan / AutoCellLibX
  AutoCellLibX: Automated Standard Cell Library Extension Based on Pattern Mining
  ☆18Updated 3 years ago
• amahzoon / genmul
  ☆18Updated 5 years ago
• scale-lab / BACS
  Benchmarks for Approximate Circuit Synthesis
  ☆17Updated 5 years ago
• lsils / benchmarks
  EPFL logic synthesis benchmarks
  ☆223Updated last month
• Yu-Maryland / MapTune
  MapTune: Advancing ASIC Technology Mapping via Reinforcement Learning Guided Library Tuning Mingju Liu, Daniel Robinson, Yingjie Li, Cunx…
  ☆22Updated 8 months ago
• JBlocklove / LLMs-for-EDA-Tutorial
  ☆55Updated 6 months ago
• lamda-bbo / Efficient-TDP
  Official implementation of DATE'25 paper "Timing-Driven Global Placement by Efficient Critical Path Extraction".
  ☆59Updated 6 months ago
• jpsety / verilog_benchmark_circuits
  EPFL and ISCAS85 combinational benchmark circuits in generic gate verilog
  ☆29Updated 5 years ago
• hkust-zhiyao / CircuitFusion
  CircuitFusion: Multimodal Circuit Representation Learning for Agile Chip Design (ICLR'25)
  ☆30Updated 8 months ago