Alternatives and similar repositories for python-deepgate

Users that are interested in python-deepgate are comparing it to the libraries listed below

• hkust-zhiyao / MasterRTL
  MasterRTL: A Pre-Synthesis PPA Estimation Framework for Any RTL Design
  ☆54Updated 3 months ago
• zshi0616 / DeepGate2
  ☆29Updated last year
• ispras / hdl-benchmarks
  Collection of digital hardware modules & projects (benchmarks)
  ☆61Updated this week
• cuhk-eda / CULS
  GPU-based logic synthesis tool
  ☆90Updated last month
• panhomyoung / phyLS
  A Logic Synthesis tool based on "Mockturtle: EPFL Logic Synthesis Library " and "ABC: System for Sequential Logic Synthesis and Formal Ve…
  ☆32Updated 2 months ago
• lamda-bbo / Open3DBench
  Official implementation of paper "Open3DBench: Open-Source Benchmark for 3D-IC Backend Implementation and PPA Evaluation".
  ☆52Updated 3 months ago
• zslwyuan / AutoCellLibX
  AutoCellLibX: Automated Standard Cell Library Extension Based on Pattern Mining
  ☆17Updated 2 years ago
• hkustgz-zhang-lab / ABCPaperCheck
  Research paper based on or related to ABC.
  ☆52Updated 2 months ago
• hkust-zhiyao / AssertLLM
  Generating Hardware Verification Assertions from Design Specifications via Multi-LLMs
  ☆38Updated 10 months ago
• Yu-Maryland / Verilog-to-PyG
  ☆24Updated last year
• yaoxufeng / RTLRewriter-Bench
  ☆36Updated last year
• santoshsmalagi / Benchmarks
  A collection of ISCAS,ITC,TAU and other Benchmark Circuits for EDA tool evaluation.
  ☆56Updated 8 months ago
• HKUSTGZ-MICS-LYU / FlattenRTL
  This is a python repo for flattening Verilog
  ☆19Updated 4 months ago
• hkust-zhiyao / RTL-Timer
  Annotating Slack Directly on Your Verilog: Fine-Grained RTL Timing Evaluation for Early Optimization
  ☆32Updated 3 months ago
• Yu-Maryland / Gamora
  Gamora: Graph Learning based Symbolic Reasoning for Large-Scale Boolean Networks (DAC'23)
  ☆50Updated 8 months ago
• rachelselinar / DREAMPlaceFPGA
  An Open-Source Analytical Placer for Large Scale Heterogeneous FPGAs using Deep-Learning Toolkit
  ☆84Updated 4 months ago
• Entropy-xcy / sns
  ☆19Updated 2 years ago
• zslwyuan / AMF-Placer
  AMF-Placer 2.0: An open-source timing-driven analytical mixed-size FPGA placer of heterogeneous resources (LUT/FF/LUTRAM/MUX/CARRY/DSP/BR…
  ☆105Updated last year
• OSCC-Project / iMap
  Logic optimization and technology mapping tool.
  ☆19Updated last year
• NVlabs / INSTA
  ☆86Updated 2 months ago
• lsils / benchmarks
  EPFL logic synthesis benchmarks
  ☆210Updated last month
• NTU-LaDS-II / FAN_ATPG
  FAN (fan-out-oriented) ATPG (Automatic Test Pattern Generation) and Fault Simulation command line tool
  ☆94Updated 2 months ago
• ABKGroup / TritonPart
  The first version of TritonPart
  ☆28Updated last year
• jpsety / verilog_benchmark_circuits
  EPFL and ISCAS85 combinational benchmark circuits in generic gate verilog
  ☆28Updated 5 years ago
• tsung-wei-huang / ece5960-physical-design
  ☆39Updated 2 years ago
• nbulsi / also
  A logic synthesis tool
  ☆80Updated last week
• scale-lab / BACS
  Benchmarks for Approximate Circuit Synthesis
  ☆17Updated 5 years ago
• Yu-Maryland / MapTune
  MapTune: Advancing ASIC Technology Mapping via Reinforcement Learning Guided Library Tuning Mingju Liu, Daniel Robinson, Yingjie Li, Cunx…
  ☆22Updated 5 months ago
• JBlocklove / LLMs-for-EDA-Tutorial
  ☆53Updated 3 months ago
• lnis-uofu / LSOracle
  IDEA project source files
  ☆108Updated last month