☆27Jun 25, 2024Updated last year
Alternatives and similar repositories for python-deepgate
Users that are interested in python-deepgate are comparing it to the libraries listed below
Sorting:
- ☆31Dec 2, 2023Updated 2 years ago
- DeepGate3 for ICCAD2024☆13May 26, 2025Updated 9 months ago
- ☆14Oct 8, 2024Updated last year
- LLM4HWDesign Starting Toolkit☆19Oct 4, 2024Updated last year
- E-Syn: E-Graph Rewriting with Technology-Aware Cost Functions for Logic Synthesis (DAC 2024)☆41Jul 17, 2024Updated last year
- GPU-based logic synthesis tool☆97Nov 27, 2025Updated 3 months ago
- OpenABC-D is a large-scale labeled dataset generated by synthesizing open source hardware IPs. This dataset can be used for various graph…☆144Jul 23, 2025Updated 7 months ago
- This is a python repo for flattening Verilog☆20Dec 19, 2025Updated 2 months ago
- Problems and Results of IWLS 2022 Programming Contest☆21Apr 12, 2025Updated 10 months ago
- Gamora: Graph Learning based Symbolic Reasoning for Large-Scale Boolean Networks (DAC'23)☆58Jan 8, 2025Updated last year
- Logic optimization and technology mapping tool.☆20Oct 12, 2023Updated 2 years ago
- Arche is a Greek word with primary senses "beginning". The repository defines a framework for technology mapping of emerging technologies…☆11May 15, 2020Updated 5 years ago
- Research paper based on or related to ABC.☆70Jan 19, 2026Updated last month
- Boosted E-Graph Extraction with Adaptive Heuristics and Exact Solving☆29Jan 7, 2026Updated last month
- Control Logic Synthesis: Drawing the Rest of the OWL☆13Jun 17, 2024Updated last year
- SIMPLE MAGIC: Synthesis and In-memory MaPping of Logic Execution for Memristor Aided loGIC☆15Jan 23, 2020Updated 6 years ago
- CircuitFusion: Multimodal Circuit Representation Learning for Agile Chip Design (ICLR'25)☆33Apr 13, 2025Updated 10 months ago
- A high-efficiency hybrid solving CEC algorithm☆14May 25, 2023Updated 2 years ago
- Arithmetic multiplier benchmarks☆12Nov 13, 2017Updated 8 years ago
- ☆17Apr 16, 2024Updated last year
- ☆59Jan 19, 2026Updated last month
- ☆13Jan 20, 2023Updated 3 years ago
- Semi-Tenser Product based SAT and AllSAT solver, where it can solve CNF and circuit input.☆17Aug 2, 2023Updated 2 years ago
- Awesome machine learning for logic synthesis☆30Sep 21, 2022Updated 3 years ago
- SpecLLM: Exploring Generation and Review of VLSI Design Specification with Large Language Model☆15Jan 29, 2024Updated 2 years ago
- A collection of ISCAS,ITC,TAU and other Benchmark Circuits for EDA tool evaluation.☆64Jan 13, 2025Updated last year
- AIGER And-Inverter-Graph Library☆97Feb 17, 2026Updated last week
- MasterRTL: A Pre-Synthesis PPA Estimation Framework for Any RTL Design☆66May 29, 2025Updated 9 months ago
- EPFL and ISCAS85 combinational benchmark circuits in generic gate verilog☆31Jan 17, 2020Updated 6 years ago
- ☆15May 24, 2023Updated 2 years ago
- Annotating Slack Directly on Your Verilog: Fine-Grained RTL Timing Evaluation for Early Optimization☆41May 29, 2025Updated 9 months ago
- Official Implementation of "Circuit Transformer: A Transformer That Preserves Logical Equivalence"☆23Mar 13, 2025Updated 11 months ago
- QuteRTL: A RTL Front-End Towards Intelligent Synthesis and Verification☆16Nov 8, 2016Updated 9 years ago
- [IJCAI 2024] QiMeng-CPU-v1: Automated CPU Design by Learning from Input-Output Examples☆27May 4, 2025Updated 9 months ago
- A Logic Synthesis tool based on "Mockturtle: EPFL Logic Synthesis Library " and "ABC: System for Sequential Logic Synthesis and Formal Ve…☆39Dec 24, 2025Updated 2 months ago
- Re-host of ISCAS89 sequential benchmark circuits in higher level verilog (without "DFF")☆15Dec 3, 2021Updated 4 years ago
- ☆20Jun 12, 2024Updated last year
- This is a repo to store circuit design datasets☆19Jan 17, 2024Updated 2 years ago
- IDEA project source files☆111Oct 15, 2025Updated 4 months ago