Alternatives and similar repositories for Design-Dataset

Users that are interested in Design-Dataset are comparing it to the libraries listed below

• HKUSTGZ-MICS-LYU / FlattenRTL
  This is a python repo for flattening Verilog
  ☆18Updated 2 months ago
• hkust-zhiyao / AssertLLM
  Generating Hardware Verification Assertions from Design Specifications via Multi-LLMs
  ☆35Updated 9 months ago
• yaoxufeng / RTLRewriter-Bench
  ☆36Updated last year
• hkust-zhiyao / MasterRTL
  MasterRTL: A Pre-Synthesis PPA Estimation Framework for Any RTL Design
  ☆50Updated 2 months ago
• pku-dasys / easymac
  ☆16Updated 3 years ago
• cornell-zhang / HOGA
  Hop-Wise Graph Attention for Scalable and Generalizable Learning on Circuits
  ☆30Updated 11 months ago
• JBlocklove / LLMs-for-EDA-Tutorial
  ☆52Updated 2 months ago
• Entropy-xcy / sns
  ☆19Updated 2 years ago
• Yu-Maryland / Gamora
  Gamora: Graph Learning based Symbolic Reasoning for Large-Scale Boolean Networks (DAC'23)
  ☆49Updated 7 months ago
• zshi0616 / python-deepgate
  ☆22Updated last year
• hkust-zhiyao / RTL-Timer
  Annotating Slack Directly on Your Verilog: Fine-Grained RTL Timing Evaluation for Early Optimization
  ☆31Updated 2 months ago
• Yu-Maryland / Verilog-to-PyG
  ☆24Updated last year
• ispras / hdl-benchmarks
  Collection of digital hardware modules & projects (benchmarks)
  ☆59Updated 2 weeks ago
• Qimeng-ICT / Qimeng-1
  ☆21Updated 3 months ago
• hkust-zhiyao / CircuitFusion
  CircuitFusion: Multimodal Circuit Representation Learning for Agile Chip Design (ICLR'25)
  ☆20Updated 3 months ago
• cuhk-eda / CULS
  GPU-based logic synthesis tool
  ☆86Updated last month
• UCLA-VAST / HARP
  ICCAD'23 Best Paper Award candidate: Robust GNN-based Representation Learning for HLS
  ☆21Updated last year
• Gy-Hu / E-Syn
  E-Syn: E-Graph Rewriting with Technology-Aware Cost Functions for Logic Synthesis (DAC 2024)
  ☆33Updated last year
• amahzoon / genmul
  ☆16Updated 4 years ago
• baichen318 / boom-explorer-public
  The open-sourced version of BOOM-Explorer
  ☆43Updated 2 years ago
• UCLA-VAST / GNN-DSE
  DAC'22 paper: "Automated Accelerator Optimization Aided by Graph Neural Networks"
  ☆40Updated last year
• OSCC-Project / iMap
  Logic optimization and technology mapping tool.
  ☆19Updated last year
• sjtu-zhao-lab / hierarchical-gnn-for-hls
  DATE'24 paper: "Hierarchical Source-to-Post-Route QoR Prediction in High-Level Synthesis with GNNs"
  ☆17Updated 7 months ago
• lamda-bbo / Open3DBench
  Official implementation of paper "Open3DBench: Open-Source Benchmark for 3D-IC Backend Implementation and PPA Evaluation".
  ☆41Updated last month
• laiyao1 / ArithTreeRL
  The release for paper "Scalable and Effective Arithmetic Tree Generation for Adder and Multiplier Designs"
  ☆13Updated 10 months ago
• rachelselinar / DREAMPlaceFPGA
  An Open-Source Analytical Placer for Large Scale Heterogeneous FPGAs using Deep-Learning Toolkit
  ☆82Updated 3 months ago
• ekiwi / rtl-repair
  Fast Symbolic Repair of Hardware Design Code
  ☆25Updated 6 months ago
• baichen318 / rl-explorer
  ☆13Updated last year
• sharc-lab / LightningSim
  A fast, accurate trace-based simulator for High-Level Synthesis.
  ☆67Updated 4 months ago
• pku-dasys / cocoon
  An infrastructure for integrated EDA
  ☆41Updated 2 years ago