HKUST-GZ-VLSI / Design-DatasetLinks
This is a repo to store circuit design datasets
☆19Updated 2 years ago
Alternatives and similar repositories for Design-Dataset
Users that are interested in Design-Dataset are comparing it to the libraries listed below
Sorting:
- Generating Hardware Verification Assertions from Design Specifications via Multi-LLMs☆48Updated last year
- This is a python repo for flattening Verilog☆20Updated last month
- CircuitFusion: Multimodal Circuit Representation Learning for Agile Chip Design (ICLR'25)☆31Updated 9 months ago
- Hop-Wise Graph Attention for Scalable and Generalizable Learning on Circuits☆34Updated last year
- ☆44Updated last year
- Gamora: Graph Learning based Symbolic Reasoning for Large-Scale Boolean Networks (DAC'23)☆55Updated last year
- MasterRTL: A Pre-Synthesis PPA Estimation Framework for Any RTL Design☆64Updated 7 months ago
- ☆18Updated 3 years ago
- Annotating Slack Directly on Your Verilog: Fine-Grained RTL Timing Evaluation for Early Optimization☆38Updated 7 months ago
- ☆20Updated 3 years ago
- ICCAD'23 Best Paper Award candidate: Robust GNN-based Representation Learning for HLS☆23Updated last year
- ☆59Updated 7 months ago
- Using e-graphs for logic synthesis☆30Updated this week
- ☆19Updated 5 years ago
- DAC'22 paper: "Automated Accelerator Optimization Aided by Graph Neural Networks"☆40Updated 2 years ago
- ☆29Updated last year
- LLM Evaluation Benchmark on Hardware Formal Verification☆35Updated 9 months ago
- ☆27Updated last year
- E-Syn: E-Graph Rewriting with Technology-Aware Cost Functions for Logic Synthesis (DAC 2024)☆41Updated last year
- Collection of digital hardware modules & projects (benchmarks)☆75Updated last month
- Logic optimization and technology mapping tool.☆20Updated 2 years ago
- The release for paper "Scalable and Effective Arithmetic Tree Generation for Adder and Multiplier Designs"☆14Updated last year
- GPU-based logic synthesis tool☆97Updated last month
- The open-sourced version of BOOM-Explorer☆46Updated 2 years ago
- Fast Symbolic Repair of Hardware Design Code☆32Updated 11 months ago
- [DATE 2022] PowerGear: Early-Stage Power Estimation in FPGA HLS via Heterogeneous Edge-Centric GNNs☆20Updated 3 years ago
- DATE'24 paper: "Hierarchical Source-to-Post-Route QoR Prediction in High-Level Synthesis with GNNs"☆19Updated last year
- ☆13Updated last year
- Benchmarks for Approximate Circuit Synthesis☆17Updated 5 years ago
- GOMIL: Global Optimization of Multiplier by Integer Linear Programming☆13Updated 4 years ago