☆50May 18, 2024Updated 2 years ago
Alternatives and similar repositories for RTLRewriter-Bench
Users that are interested in RTLRewriter-Bench are comparing it to the libraries listed below. We may earn a commission when you buy through links labeled 'Ad' on this page.
Sorting:
- Annotating Slack Directly on Your Verilog: Fine-Grained RTL Timing Evaluation for Early Optimization☆49May 29, 2025Updated last year
- Contract-Aware RTL Code Generation Agents with Temporal Tracing, Slicing and Formal Verification☆26Jan 28, 2026Updated 8 months ago
- Collection for submission (Hardware Model Checking Benchmark)☆13Nov 9, 2025Updated 11 months ago
- Random Generator of Btor2 Files☆10Sep 2, 2023Updated 3 years ago
- ☆63Jul 13, 2026Updated 2 months ago
- Managed hosting for WordPress and PHP on Cloudways • AdManaged hosting for WordPress, Magento, Laravel, or PHP apps, on multiple cloud providers. Deploy in minutes on Cloudways by DigitalOcean.
- Code for paper 'ReChisel: Effective Automatic Chisel Code Generation by LLM with Reflection'☆16Jul 4, 2025Updated last year
- PRO-V: An Efficient Program Generation Multi-Agent System for Automatic RTL Verification☆36Dec 11, 2025Updated 10 months ago
- A Lean-embedded framework to verify Verilog modules☆16Oct 6, 2026Updated last week
- ☆18Jul 26, 2026Updated 2 months ago
- FPGA synthesis tool powered by equality saturation and program synthesis.☆15Jan 9, 2026Updated 9 months ago
- OriGen: Enhancing RTL Code Generation with Code-to-Code Augmentation and Self-Reflection(ICCAD 2024)☆35Oct 20, 2024Updated last year
- ☆13Jan 20, 2023Updated 3 years ago
- A collection of datapath circuit design and verification benchmarks☆19Aug 24, 2026Updated last month
- Automatic generation of architecture-level models for hardware from its RTL design.☆17Apr 12, 2023Updated 3 years ago
- GPUs on demand by Runpod - Special Offer Available • AdRun AI, ML, and HPC workloads on powerful cloud GPUs—without limits or wasted spend. Deploy GPUs in under a minute and pay by the second.
- FYP on using e-graphs to solve smt bitvector problems☆16Jun 24, 2025Updated last year
- ☆19May 24, 2023Updated 3 years ago
- work in progress, playing around with btor2 in rust☆16Oct 2, 2026Updated last week
- Arithmetic multiplier benchmarks☆12Nov 13, 2017Updated 8 years ago
- BTOR2 MLIR project☆26Jan 17, 2024Updated 2 years ago
- E-morphic: Scalable Equality Saturation for Structural Exploration in Logic Synthesis (DAC2025)☆32Jun 23, 2025Updated last year
- APS: An open-source toolchain towards agile processor specialization based on MLIR☆22Jan 17, 2026Updated 8 months ago
- ☆238Jun 8, 2026Updated 4 months ago
- LLM Evaluation Benchmark on Hardware Formal Verification☆45Apr 3, 2025Updated last year
- Proton VPN Special Offer - Get 70% off • AdSpecial partner offer. Trusted by over 100 million users worldwide. Tested, Approved and Recommended by Experts.
- MapTune: Advancing ASIC Technology Mapping via Reinforcement Learning Guided Library Tuning Mingju Liu, Daniel Robinson, Yingjie Li, Cunx…☆30Apr 9, 2025Updated last year
- Collection of utlities for writing parsers. Includes a fast DIMACS CNF parser.☆15Nov 19, 2024Updated last year
- MasterRTL: A Pre-Synthesis PPA Estimation Framework for Any RTL Design☆79May 29, 2025Updated last year
- Yosys RTLIL dialect for MLIR☆25Jun 12, 2025Updated last year
- E-Syn: E-Graph Rewriting with Technology-Aware Cost Functions for Logic Synthesis (DAC 2024)☆46Jul 17, 2024Updated 2 years ago
- A fork of the Kissat SAT solver with additional features. Supports incremental solving.☆17Aug 13, 2022Updated 4 years ago
- Fast Symbolic Repair of Hardware Design Code☆40Jan 20, 2025Updated last year
- [DATE 2025] haven: hallucination-mitigated llm for verilog code generation aligned with hdl engineers☆44Jul 9, 2025Updated last year
- An advanced circuit-based sat solver☆39Feb 24, 2025Updated last year
- Virtual machines for every use case on DigitalOcean • AdGet dependable uptime with 99.99% SLA, simple security tools, and predictable monthly pricing with DigitalOcean's virtual machines, called Droplets.
- Refreshing automation for inductive equational proofs using e-graphs☆28Jul 7, 2024Updated 2 years ago
- TuRTLe: A Unified Evaluation of LLMs for RTL Generation 🐢 (MLCAD 2025, ACM TODAES 2026)☆51Jul 22, 2026Updated 2 months ago
- ☆58Jan 6, 2026Updated 9 months ago
- RTL-Repo: A Benchmark for Evaluating LLMs on Large-Scale RTL Design Projects - IEEE LAD'24☆35Jun 5, 2024Updated 2 years ago
- The first large scale formally verified reasoning dataset for Verilog☆25May 16, 2025Updated last year
- ☆20Oct 2, 2026Updated last week
- Verilog evaluation benchmark for large language model☆481Jul 14, 2025Updated last year