Alternatives and similar repositories for easymac

Users that are interested in easymac are comparing it to the libraries listed below

• zlinaf / PowerGear
  [DATE 2022] PowerGear: Early-Stage Power Estimation in FPGA HLS via Heterogeneous Edge-Centric GNNs
  ☆18Updated 3 years ago
• UT-LCA / ML4Accel-Dataset
  Dataset for ML-guided Accelerator Design
  ☆37Updated 7 months ago
• UCLA-VAST / GNN-DSE
  DAC'22 paper: "Automated Accelerator Optimization Aided by Graph Neural Networks"
  ☆40Updated last year
• UCLA-VAST / HARP
  ICCAD'23 Best Paper Award candidate: Robust GNN-based Representation Learning for HLS
  ☆20Updated last year
• Entropy-xcy / sns
  ☆18Updated 2 years ago
• Yu-Maryland / Verilog-to-PyG
  ☆25Updated last year
• cornell-zhang / HOGA
  Hop-Wise Graph Attention for Scalable and Generalizable Learning on Circuits
  ☆30Updated 10 months ago
• hkust-zhiyao / MasterRTL
  MasterRTL: A Pre-Synthesis PPA Estimation Framework for Any RTL Design
  ☆50Updated 3 weeks ago
• HKUST-GZ-VLSI / Design-Dataset
  This is a repo to store circuit design datasets
  ☆18Updated last year
• synergy-noc-generators / Proteus
  ☆10Updated 2 years ago
• UCLA-VAST / AutoDSE
  ACM TODAES Best Paper Award, 2022
  ☆25Updated last year
• VeriGOOD-ML / public
  ☆59Updated last month
• Yu-Maryland / Gamora
  Gamora: Graph Learning based Symbolic Reasoning for Large-Scale Boolean Networks (DAC'23)
  ☆50Updated 5 months ago
• tancheng / mlir-cgra
  An MLIR dialect to enable the efficient acceleration of ML model on CGRAs.
  ☆59Updated 8 months ago
• ispras / hdl-benchmarks
  Collection of digital hardware modules & projects (benchmarks)
  ☆59Updated last month
• yzwangfeng / reram-synthesis
  A synthesis flow for hybrid processing-in-RRAM modes
  ☆12Updated 3 years ago
• SJTU-ECTL / GOMIL
  GOMIL: Global Optimization of Multiplier by Integer Linear Programming
  ☆13Updated 3 years ago
• diwu1990 / uSystolic-Sim
  A systolic array simulator for multi-cycle MACs and varying-byte words, with the paper accepted to HPCA 2022.
  ☆79Updated 3 years ago
• jianyicheng / DSS
  DASS HLS Compiler
  ☆29Updated last year
• scale-lab / BACS
  Benchmarks for Approximate Circuit Synthesis
  ☆16Updated 4 years ago
• hngenc / stellar
  ☆30Updated 7 months ago
• HKUSTGZ-MICS-LYU / FlattenRTL
  This is a python repo for flattening Verilog
  ☆18Updated last month
• baichen318 / boom-explorer-public
  The open-sourced version of BOOM-Explorer
  ☆40Updated 2 years ago
• UIUC-ChenLab / ScaleHLS-HIDA
  ☆55Updated 3 months ago
• RipperJ / FADO
  [FPGA 2023] FADO: Floorplan-Aware Directive Optimization for High-Level Synthesis Designs on Multi-Die FPGAs
  ☆24Updated 2 years ago
• sharc-lab / LightningSim
  A fast, accurate trace-based simulator for High-Level Synthesis.
  ☆47Updated 2 months ago
• arc-research-lab / AIM
  AIM: Accelerating Arbitrary-precision Integer Multiplication on Heterogeneous Reconfigurable Computing Platform Versal ACAP (Full Paper a…
  ☆23Updated last month
• PolyArch / dsagen2
  Domain-Specific Architecture Generator 2
  ☆21Updated 2 years ago
• maestro-project / magma
  ☆16Updated 3 years ago
• sjtu-zhao-lab / hierarchical-gnn-for-hls
  DATE'24 paper: "Hierarchical Source-to-Post-Route QoR Prediction in High-Level Synthesis with GNNs"
  ☆17Updated 6 months ago