hkust-zhiyao / CircuitFusionLinks
CircuitFusion: Multimodal Circuit Representation Learning for Agile Chip Design (ICLR'25)
☆26Updated 7 months ago
Alternatives and similar repositories for CircuitFusion
Users that are interested in CircuitFusion are comparing it to the libraries listed below
Sorting:
- Generating Hardware Verification Assertions from Design Specifications via Multi-LLMs☆40Updated last year
- Gamora: Graph Learning based Symbolic Reasoning for Large-Scale Boolean Networks (DAC'23)☆54Updated 10 months ago
- ☆41Updated last year
- This is a repo to store circuit design datasets☆19Updated last year
- ☆16Updated 2 years ago
- Hop-Wise Graph Attention for Scalable and Generalizable Learning on Circuits☆33Updated last year
- LLM Evaluation Benchmark on Hardware Formal Verification☆33Updated 7 months ago
- ☆20Updated 3 years ago
- ☆31Updated 7 months ago
- ☆25Updated last year
- Logic optimization and technology mapping tool.☆19Updated 2 years ago
- ☆55Updated 5 months ago
- MasterRTL: A Pre-Synthesis PPA Estimation Framework for Any RTL Design☆58Updated 5 months ago
- This is a python repo for flattening Verilog☆20Updated 6 months ago
- ☆27Updated last year
- This is an official implementation for "DeepGate: Learning Neural Representations of Logic Gates".☆24Updated 2 years ago
- Fast Symbolic Repair of Hardware Design Code☆28Updated 9 months ago
- E-Syn: E-Graph Rewriting with Technology-Aware Cost Functions for Logic Synthesis (DAC 2024)☆38Updated last year
- NetTAG: A Multimodal RTL-and-Layout-Aligned Netlist Foundation Model via Text-Attributed Graph (DAC'25)☆18Updated 2 months ago
- ☆18Updated 4 years ago
- ☆12Updated 2 years ago
- ☆21Updated 9 months ago
- The release for paper "Scalable and Effective Arithmetic Tree Generation for Adder and Multiplier Designs"☆13Updated last year
- ICCAD'23 Best Paper Award candidate: Robust GNN-based Representation Learning for HLS☆21Updated last year
- DeepIC3: Guiding IC3 Algorithms by Graph Neural Network Clause Prediction (ASP-DAC 2024)☆11Updated 2 years ago
- ☆31Updated last year
- MapTune: Advancing ASIC Technology Mapping via Reinforcement Learning Guided Library Tuning Mingju Liu, Daniel Robinson, Yingjie Li, Cunx…☆22Updated 7 months ago
- Collection of digital hardware modules & projects (benchmarks)☆69Updated last week
- Annotating Slack Directly on Your Verilog: Fine-Grained RTL Timing Evaluation for Early Optimization☆34Updated 5 months ago
- GNN-RE datasets for circuit recognition☆55Updated 2 years ago