(WIP) Open-source Rust gate-level EDA infrastructure: parsers and databases
☆21May 2, 2026Updated 3 months ago
Alternatives and similar repositories for eda-infra-rs
Users that are interested in eda-infra-rs are comparing it to the libraries listed below. We may earn a commission when you buy through links labeled 'Ad' on this page.
Sorting:
- ☆13Jan 20, 2023Updated 3 years ago
- APS: An open-source toolchain towards agile processor specialization based on MLIR☆20Jan 17, 2026Updated 7 months ago
- A collection of datapath circuit design and verification benchmarks☆19Updated this week
- GL0AM GPU Accelerated Gate Level Logic Simulator☆31Feb 11, 2026Updated 6 months ago
- GPU-based logic synthesis tool☆110Mar 31, 2026Updated 4 months ago
- Serverless GPU API endpoints on Runpod - Get Bonus Credits • AdSkip the infrastructure headaches. Auto-scaling, pay-as-you-go, no-ops approach lets you focus on innovating your application.
- Collection for submission (Hardware Model Checking Benchmark)☆13Nov 9, 2025Updated 9 months ago
- Annotating Slack Directly on Your Verilog: Fine-Grained RTL Timing Evaluation for Early Optimization☆49May 29, 2025Updated last year
- Using e-graphs for logic synthesis (ICCAD'25)☆36Updated this week
- DeepIC3: Guiding IC3 Algorithms by Graph Neural Network Clause Prediction (ASP-DAC 2024)☆14Nov 2, 2023Updated 2 years ago
- Collection of utlities for writing parsers. Includes a fast DIMACS CNF parser.☆15Nov 19, 2024Updated last year
- Boosted E-Graph Extraction with Adaptive Heuristics and Exact Solving☆30Jan 7, 2026Updated 7 months ago
- RTLMeter benchmark suite☆32Updated this week
- Exact Symbolic Reasoning via Boolean Equality Saturation☆25Jan 7, 2026Updated 7 months ago
- Random Generator of Btor2 Files☆10Sep 2, 2023Updated 2 years ago
- GPU virtual machines on DigitalOcean Gradient AI • AdGet to production fast with high-performance AMD and NVIDIA GPUs you can spin up in seconds. The definition of operational simplicity.
- This is a python repo for flattening Verilog☆20Dec 19, 2025Updated 8 months ago
- BTOR2 MLIR project☆26Jan 17, 2024Updated 2 years ago
- ☆31Dec 8, 2025Updated 8 months ago
- E-Graphs, natively in MLIR☆36Updated this week
- A word hashing method based on vectors of letter n-grams. Currently transforms text into sequences of numbers.☆10Feb 27, 2018Updated 8 years ago
- Open-source RTL logic simulator with CUDA acceleration☆294Sep 30, 2025Updated 10 months ago
- E-morphic: Scalable Equality Saturation for Structural Exploration in Logic Synthesis (DAC2025)☆31Jun 23, 2025Updated last year
- ☆17Apr 19, 2026Updated 4 months ago
- Differentiable Combinatorial Scheduling at Scale (ICML'24). Mingju Liu, Yingjie Li, Jiaqi Yin, Zhiru Zhang, Cunxi Yu.☆24Oct 31, 2024Updated last year
- Managed hosting for WordPress and PHP on Cloudways • AdManaged hosting for WordPress, Magento, Laravel, or PHP apps, on multiple cloud providers. Deploy in minutes on Cloudways by DigitalOcean.
- Fully defined liberty (std. cells in VLSI) data structure, efficient parser & formatter☆28Feb 24, 2026Updated 6 months ago
- Gate-level timing estimation toolkit☆25Apr 11, 2022Updated 4 years ago
- FPGA 2025 SAT Accel: A modern SAT Solver on FPGA Repository☆14Mar 13, 2025Updated last year
- ☆109Jun 20, 2025Updated last year
- An advanced circuit-based sat solver☆39Feb 24, 2025Updated last year
- Fast Symbolic Repair of Hardware Design Code☆40Jan 20, 2025Updated last year
- TAIDL: Tensor Accelerator ISA Definition Language☆19Apr 28, 2026Updated 4 months ago
- Problems and Results of IWLS 2022 Programming Contest☆24Apr 12, 2025Updated last year
- ☆18Feb 25, 2026Updated 6 months ago
- Managed hosting for WordPress and PHP on Cloudways • AdManaged hosting for WordPress, Magento, Laravel, or PHP apps, on multiple cloud providers. Deploy in minutes on Cloudways by DigitalOcean.
- ☆17Feb 5, 2026Updated 6 months ago
- This is a repo to store circuit design datasets☆19Jan 17, 2024Updated 2 years ago
- MasterRTL: A Pre-Synthesis PPA Estimation Framework for Any RTL Design☆78May 29, 2025Updated last year
- 21st century electronic design automation tools, written in Rust.☆37Updated this week
- FYP on using e-graphs to solve smt bitvector problems☆16Jun 24, 2025Updated last year
- ANSI-C benchmarks generated from Verilog RTL circuits with safety assertions. Used for Formal Property Verification.☆17Dec 1, 2018Updated 7 years ago
- A Python library for working with logic networks, synthesis, and optimization.☆88Updated this week