hkust-zhiyao / SpecLLMLinks
SpecLLM: Exploring Generation and Review of VLSI Design Specification with Large Language Model
☆15Updated last year
Alternatives and similar repositories for SpecLLM
Users that are interested in SpecLLM are comparing it to the libraries listed below
Sorting:
- MasterRTL: A Pre-Synthesis PPA Estimation Framework for Any RTL Design☆56Updated 4 months ago
- ☆19Updated 2 years ago
- Generating Hardware Verification Assertions from Design Specifications via Multi-LLMs☆38Updated 11 months ago
- An open-source benchmark for generating design RTL with natural language☆133Updated 11 months ago
- 🕹 OpenPARF: An Open-Source Placement and Routing Framework for Large-Scale Heterogeneous FPGAs with Deep Learning Toolkit☆155Updated 5 months ago
- The release for paper "Scalable and Effective Arithmetic Tree Generation for Adder and Multiplier Designs"☆14Updated last year
- ☆40Updated last year
- Collection of digital hardware modules & projects (benchmarks)☆62Updated last month
- CircuitFusion: Multimodal Circuit Representation Learning for Agile Chip Design (ICLR'25)☆25Updated 5 months ago
- AutoCellLibX: Automated Standard Cell Library Extension Based on Pattern Mining☆17Updated 2 years ago
- ☆54Updated 4 months ago
- ☆23Updated last year
- ☆28Updated 6 months ago
- This is a repo to store circuit design datasets☆18Updated last year
- This is a python repo for flattening Verilog☆19Updated 4 months ago
- GPU-based logic synthesis tool☆90Updated 2 months ago
- AMF-Placer 2.0: An open-source timing-driven analytical mixed-size FPGA placer of heterogeneous resources (LUT/FF/LUTRAM/MUX/CARRY/DSP/BR…☆105Updated last year
- ☆18Updated 4 years ago
- Logic optimization and technology mapping tool.☆19Updated last year
- Dr. CU, VLSI Detailed Routing Tool Developed by CUHK☆137Updated 2 years ago
- Benchmarks for Approximate Circuit Synthesis☆17Updated 5 years ago
- OpenABC-D is a large-scale labeled dataset generated by synthesizing open source hardware IPs. This dataset can be used for various graph…☆133Updated 2 months ago
- FAN (fan-out-oriented) ATPG (Automatic Test Pattern Generation) and Fault Simulation command line tool☆96Updated 3 months ago
- Annotating Slack Directly on Your Verilog: Fine-Grained RTL Timing Evaluation for Early Optimization☆32Updated 4 months ago
- Gamora: Graph Learning based Symbolic Reasoning for Large-Scale Boolean Networks (DAC'23)☆52Updated 9 months ago
- ☆184Updated 11 months ago
- EPFL and ISCAS85 combinational benchmark circuits in generic gate verilog☆28Updated 5 years ago
- CUGR, VLSI Global Routing Tool Developed by CUHK☆139Updated 2 years ago
- MapTune: Advancing ASIC Technology Mapping via Reinforcement Learning Guided Library Tuning Mingju Liu, Daniel Robinson, Yingjie Li, Cunx…☆22Updated 6 months ago
- ☆24Updated last year