SpecLLM: Exploring Generation and Review of VLSI Design Specification with Large Language Model
☆15Jan 29, 2024Updated 2 years ago
Alternatives and similar repositories for SpecLLM
Users that are interested in SpecLLM are comparing it to the libraries listed below
Sorting:
- PANDA: Architecture-Level Power Evaluation by Unifying Analytical and Machine Learning Solutions☆17Dec 18, 2023Updated 2 years ago
- Generating Hardware Verification Assertions from Design Specifications via Multi-LLMs☆50Oct 28, 2024Updated last year
- NetTAG: A Multimodal RTL-and-Layout-Aligned Netlist Foundation Model via Text-Attributed Graph (DAC'25)☆24Dec 21, 2025Updated 2 months ago
- A circuit-element level explainer to explain machine learning model's prediction on chip layouts.☆18Oct 30, 2023Updated 2 years ago
- Annotating Slack Directly on Your Verilog: Fine-Grained RTL Timing Evaluation for Early Optimization☆42May 29, 2025Updated 9 months ago
- An open-source benchmark for generating design RTL with natural language☆162Nov 8, 2024Updated last year
- MasterRTL: A Pre-Synthesis PPA Estimation Framework for Any RTL Design☆66May 29, 2025Updated 9 months ago
- CircuitFusion: Multimodal Circuit Representation Learning for Agile Chip Design (ICLR'25)☆33Apr 13, 2025Updated 10 months ago
- RISC-V Formal in Chisel☆13Apr 9, 2024Updated last year
- ☆30Apr 23, 2024Updated last year
- ☆13Jan 20, 2023Updated 3 years ago
- A new LLM solution for RTL code generation, achieving state-of-the-art performance in non-commercial solutions and outperforming GPT-3.5.☆255Feb 9, 2025Updated last year
- DATE'24 paper: "Hierarchical Source-to-Post-Route QoR Prediction in High-Level Synthesis with GNNs"☆20Dec 10, 2024Updated last year
- This is a repo to store circuit design datasets☆19Jan 17, 2024Updated 2 years ago
- A Formal Verification Framework for Chisel☆19Apr 9, 2024Updated last year
- ☆19Aug 30, 2020Updated 5 years ago
- Logic optimization and technology mapping tool.☆20Oct 12, 2023Updated 2 years ago
- This repository is compilation of basics of System Verilog Assertions in context of formal verification☆24Mar 7, 2019Updated 7 years ago
- ☆11Nov 22, 2024Updated last year
- ☆27Jun 25, 2024Updated last year
- Demos from Ignite 2017☆11Oct 23, 2017Updated 8 years ago
- RTL-to-Vector-to-GDS☆67Dec 5, 2025Updated 3 months ago
- E-Syn: E-Graph Rewriting with Technology-Aware Cost Functions for Logic Synthesis (DAC 2024)☆41Jul 17, 2024Updated last year
- A minimal bash tool to convert video files to any other supported media files using yt-dlp and ffmpeg.☆22Jan 11, 2026Updated last month
- ☆13Jul 22, 2022Updated 3 years ago
- Image classification on custom dataset☆15Oct 13, 2023Updated 2 years ago
- Toolkit for Dynamic Python code manipulations☆11Oct 19, 2024Updated last year
- Verilog evaluation benchmark for large language model☆381Jul 14, 2025Updated 7 months ago
- Unofficial mirror of sourceware binutils-gdb repository. Updated daily.☆11Mar 21, 2023Updated 2 years ago
- ☆14Jan 11, 2021Updated 5 years ago
- CS 380D Distributed Systems at UT Austin with Vijay Chidambaram☆12Oct 19, 2023Updated 2 years ago
- ☆13Sep 5, 2024Updated last year
- Random Generator of Btor2 Files☆10Sep 2, 2023Updated 2 years ago
- C to LLVM / Python compiler☆10Jan 17, 2017Updated 9 years ago
- Hi, Spring fans! In this installment we look at one of my favorite paradigms in Java 21 and later: Data Oriented Programming☆11Jul 9, 2024Updated last year
- ☆11Mar 5, 2025Updated last year
- Repository containing lectures from 2023 Machine Learning course☆11Mar 14, 2023Updated 2 years ago
- A generic data structures and algorithms library using C☆12Nov 13, 2022Updated 3 years ago
- My own lectures on quantum optics and quantum computations (in Russian)☆13Dec 10, 2024Updated last year