[DATE 2022] PowerGear: Early-Stage Power Estimation in FPGA HLS via Heterogeneous Edge-Centric GNNs
☆22May 11, 2026Updated last month
Alternatives and similar repositories for PowerGear
Users that are interested in PowerGear are comparing it to the libraries listed below. We may earn a commission when you buy through links labeled 'Ad' on this page.
Sorting:
- An end-to-end GCN inference accelerator written in HLS☆18Apr 5, 2022Updated 4 years ago
- High-Level Synthesis Performance Prediction using GNNs: Benchmarking, Modeling, and Advancing☆54Jun 6, 2024Updated 2 years ago
- ICCAD'23 Best Paper Award candidate: Robust GNN-based Representation Learning for HLS☆27May 23, 2024Updated 2 years ago
- [TRETS'23, FPT'20] CHIP-KNN: Configurable and HIgh-Performance K-Nearest Neighbors Accelerator on Cloud FPGAs☆19Apr 9, 2024Updated 2 years ago
- Dataset for ML-guided Accelerator Design☆45Nov 18, 2024Updated last year
- Deploy open-source AI quickly and easily - Special Bonus Offer • AdRunpod Hub is built for open source. One-click deployment and autoscaling endpoints without provisioning your own infrastructure.
- ☆16Apr 10, 2023Updated 3 years ago
- HLSFactory: A Framework Empowering High-Level Synthesis Datasets for Machine Learning and Beyond☆53Mar 31, 2026Updated 2 months ago
- DAC'22 paper: "Automated Accelerator Optimization Aided by Graph Neural Networks"☆41Oct 3, 2023Updated 2 years ago
- GPU-enabled Hardware Fuzzer using Genetic Algorithm☆20Jul 12, 2023Updated 2 years ago
- ☆18Feb 3, 2022Updated 4 years ago
- [ICASSP'20] DNN-Chip Predictor: An Analytical Performance Predictor for DNN Accelerators with Various Dataflows and Hardware Architecture…☆25Oct 1, 2022Updated 3 years ago
- ☆37Jan 20, 2022Updated 4 years ago
- ☆14Apr 8, 2025Updated last year
- This codes presents examples of constructing primitives for data structures with Hyperdimensional Computing/Vector Symbolic Architectures☆16Jun 4, 2021Updated 5 years ago
- Deploy to Railway using AI coding agents - Free Credits Offer • AdUse Claude Code, Codex, OpenCode, and more. Autonomous software development now has the infrastructure to match with Railway.
- An HBM FPGA based SpMV Accelerator☆18Aug 29, 2024Updated last year
- A FPGA-based neural network inference accelerator, which won the third place in DAC-SDC☆28May 11, 2022Updated 4 years ago
- AMD HPC Research Fund Cloud☆20Jun 3, 2026Updated 2 weeks ago
- MasterRTL: A Pre-Synthesis PPA Estimation Framework for Any RTL Design☆72May 29, 2025Updated last year
- DATE'24 paper: "Hierarchical Source-to-Post-Route QoR Prediction in High-Level Synthesis with GNNs"☆21Dec 10, 2024Updated last year
- Automatic Test Pattern Generation using PODEM algorithm☆15May 12, 2014Updated 12 years ago
- [ASAP 2020; FPGA 2020] Hardware architecture to accelerate GNNs (common IP modules for minibatch training and full batch inference)☆43Mar 30, 2021Updated 5 years ago
- Implementation of Pythia: A Customizable Hardware Prefetching Framework Using Online Reinforcement Learning in Chisel HDL. To know more, …☆18Oct 9, 2021Updated 4 years ago
- Research project from UCI's AICPS lab: using GNNs to enable hardware security and prevent hardware trojans☆10Mar 31, 2021Updated 5 years ago
- Wordpress hosting with auto-scaling - Free Trial Offer • AdFully Managed hosting for WordPress and WooCommerce businesses that need reliable, auto-scalable performance. Cloudways SafeUpdates now available.
- [DAC2024] Explainable Fuzzy Neural Network with Multi-Fidelity Reinforcement Learning for Micro-Architecture Design Space Exploration☆10Oct 31, 2024Updated last year
- [FPL 2021] SyncNN: Evaluating and Accelerating Spiking Neural Networks on FPGAs.☆64Jul 28, 2021Updated 4 years ago
- Systolic Three Matrix Multiplier for Graph Convolutional Networks using High Level Synthesis☆24Jul 29, 2022Updated 3 years ago
- PyTorch implementation of DiracDeltaNet from paper Synetgy: Algorithm-hardware Co-design for ConvNet Accelerators on Embedded FPGAs☆33May 30, 2019Updated 7 years ago
- RTL implementation of a ray-tracing GPU☆16Dec 18, 2012Updated 13 years ago
- NATSA is the first near-data-processing accelerator for time series analysis based on the Matrix Profile (SCRIMP) algorithm. NATSA exploi…☆16Jun 14, 2023Updated 3 years ago
- An FPGA accelerator for general-purpose Sparse-Matrix Dense-Matrix Multiplication (SpMM).☆94Jul 26, 2024Updated last year
- [FPGA 2020] Open sourced implementation for the ACM/SIGDA FPGA '20 paper titled "GraphACT: Accelerating GCN Training on CPU-FPGA Heteroge…☆19Mar 6, 2021Updated 5 years ago
- ☆43Oct 10, 2025Updated 8 months ago
- Simple, predictable pricing with DigitalOcean hosting • AdAlways know what you'll pay with monthly caps and flat pricing. Enterprise-grade infrastructure trusted by 600k+ customers.
- CORE-V MCU UVM Environment and Test Bench☆26Jul 19, 2024Updated last year
- Implementation of paper "GraphACT: Accelerating GCN Training on CPU-FPGA Heterogeneous Platform".☆12Jun 25, 2020Updated 5 years ago
- Template for project1 TPU☆23May 1, 2021Updated 5 years ago
- Must-read papers on Graph Neural Networks (GNNs) for Integrated Circuits (ICs) design, security and reliability.☆88Jul 10, 2025Updated 11 months ago
- Examples illustrating usage of the rocBLAS library☆17Aug 12, 2024Updated last year
- Discussion section materials for COMP SCI 537 2021 Spring at the University of Wisconsin-Madison.☆15Apr 21, 2021Updated 5 years ago
- JEDI-net: a jet identification algorithm based on interaction networks☆10Aug 16, 2020Updated 5 years ago