hkust-zhiyao / AssertLLM
Generating Hardware Verification Assertions from Design Specifications via Multi-LLMs
☆26Updated 5 months ago
Alternatives and similar repositories for AssertLLM:
Users that are interested in AssertLLM are comparing it to the libraries listed below
- MasterRTL: A Pre-Synthesis PPA Estimation Framework for Any RTL Design☆44Updated 6 months ago
- Collection of digital hardware modules & projects (benchmarks)☆52Updated 4 months ago
- This is a python repo for flattening Verilog☆16Updated 2 months ago
- ☆15Updated 2 years ago
- Annotating Slack Directly on Your Verilog: Fine-Grained RTL Timing Evaluation for Early Optimization☆22Updated 8 months ago
- ☆22Updated 9 months ago
- Research paper based on or related to ABC.☆32Updated 3 weeks ago
- ☆25Updated 11 months ago
- AutoSVA is a tool to automatically generate formal testbenches for unit-level RTL verification. The goal is to, based on annotations made…☆80Updated last year
- An open-source benchmark for generating design RTL with natural language☆97Updated 4 months ago
- Gamora: Graph Learning based Symbolic Reasoning for Large-Scale Boolean Networks (DAC'23)☆49Updated 2 months ago
- Dataset for ML-guided Accelerator Design☆36Updated 4 months ago
- PANDA: Architecture-Level Power Evaluation by Unifying Analytical and Machine Learning Solutions☆15Updated last year
- The open-sourced version of BOOM-Explorer☆39Updated last year
- A collection of ISCAS,ITC,TAU and other Benchmark Circuits for EDA tool evaluation.☆44Updated 2 months ago
- Generator of arithmetic circuits (multipliers, adders) and approximate circuits☆31Updated 2 months ago
- ☆51Updated 5 months ago
- AutoCellLibX: Automated Standard Cell Library Extension Based on Pattern Mining☆13Updated 2 years ago
- ☆28Updated 10 months ago
- EPFL and ISCAS85 combinational benchmark circuits in generic gate verilog☆25Updated 5 years ago
- This is a repo to store circuit design datasets☆16Updated last year
- ☆16Updated 3 years ago
- Fast Symbolic Repair of Hardware Design Code☆22Updated 2 months ago
- A Logic Synthesis tool based on "Mockturtle: EPFL Logic Synthesis Library " and "ABC: System for Sequential Logic Synthesis and Formal Ve…☆25Updated 2 weeks ago
- ☆21Updated last month
- An Open-Source Analytical Placer for Large Scale Heterogeneous FPGAs using Deep-Learning Toolkit☆79Updated 2 months ago
- ☆16Updated 4 years ago
- GOMIL: Global Optimization of Multiplier by Integer Linear Programming☆13Updated 3 years ago
- AMF-Placer 2.0: An open-source timing-driven analytical mixed-size FPGA placer of heterogeneous resources (LUT/FF/LUTRAM/MUX/CARRY/DSP/BR…☆101Updated last year
- E-Syn: E-Graph Rewriting with Technology-Aware Cost Functions for Logic Synthesis (DAC 2024)☆28Updated 8 months ago