Alternatives and similar repositories for Verilog-to-PyG

Users that are interested in Verilog-to-PyG are comparing it to the libraries listed below

• Yu-Maryland / Gamora
  Gamora: Graph Learning based Symbolic Reasoning for Large-Scale Boolean Networks (DAC'23)
  ☆50Updated 6 months ago
• ispras / hdl-benchmarks
  Collection of digital hardware modules & projects (benchmarks)
  ☆59Updated last week
• hkust-zhiyao / MasterRTL
  MasterRTL: A Pre-Synthesis PPA Estimation Framework for Any RTL Design
  ☆52Updated last month
• rachelselinar / DREAMPlaceFPGA
  An Open-Source Analytical Placer for Large Scale Heterogeneous FPGAs using Deep-Learning Toolkit
  ☆82Updated 2 months ago
• cuhk-eda / CULS
  GPU-based logic synthesis tool
  ☆83Updated 3 weeks ago
• scale-lab / BACS
  Benchmarks for Approximate Circuit Synthesis
  ☆16Updated 4 years ago
• Entropy-xcy / sns
  ☆18Updated 2 years ago
• cure-lab / DeepGate2
  ☆15Updated 2 years ago
• zshi0616 / python-deepgate
  ☆22Updated last year
• lydiawunan / HLS-Perf-Prediction-with-GNNs
  High-Level Synthesis Performance Prediction using GNNs: Benchmarking, Modeling, and Advancing
  ☆51Updated last year
• IntelLabs / FloorSet
  ☆73Updated last month
• HKUSTGZ-MICS-LYU / FlattenRTL
  This is a python repo for flattening Verilog
  ☆18Updated 2 months ago
• JBlocklove / LLMs-for-EDA-Tutorial
  ☆52Updated last month
• OSCC-Project / iMap
  Logic optimization and technology mapping tool.
  ☆19Updated last year
• pku-dasys / easymac
  ☆16Updated 3 years ago
• UT-LCA / ML4Accel-Dataset
  Dataset for ML-guided Accelerator Design
  ☆37Updated 7 months ago
• ABKGroup / TritonPart
  The first version of TritonPart
  ☆27Updated last year
• zlinaf / PowerGear
  [DATE 2022] PowerGear: Early-Stage Power Estimation in FPGA HLS via Heterogeneous Edge-Centric GNNs
  ☆18Updated 3 years ago
• TILOS-AI-Institute / MLCAD-2023-FPGA-Macro-Placement-Contest
  ☆29Updated last year
• NVlabs / CircuitOps
  ☆86Updated 3 weeks ago
• zslwyuan / AMF-Placer
  AMF-Placer 2.0: An open-source timing-driven analytical mixed-size FPGA placer of heterogeneous resources (LUT/FF/LUTRAM/MUX/CARRY/DSP/BR…
  ☆105Updated last year
• cure-lab / DeepGate
  This is an official implementation for "DeepGate: Learning Neural Representations of Logic Gates".
  ☆22Updated 2 years ago
• ASU-VDA-Lab / ASP-DAC24-Tutorial
  This GitHub repo is for the OpenROAD and CircuitOps Tutorial at ASP-DAC 2024
  ☆51Updated 5 months ago
• hkust-zhiyao / AssertLLM
  Generating Hardware Verification Assertions from Design Specifications via Multi-LLMs
  ☆34Updated 8 months ago
• ieee-ceda-datc / RDF-2019
  DATC RDF
  ☆51Updated 4 years ago
• ehw-fit / ariths-gen
  Generator of arithmetic circuits (multipliers, adders) and approximate circuits
  ☆35Updated 5 months ago
• zshi0616 / DeepGate2
  ☆28Updated last year
• jinwookjungs / datc_robust_design_flow
  DATC Robust Design Flow.
  ☆37Updated 5 years ago
• zslwyuan / AutoCellLibX
  AutoCellLibX: Automated Standard Cell Library Extension Based on Pattern Mining
  ☆15Updated 2 years ago
• SJTU-ECTL / GOMIL
  GOMIL: Global Optimization of Multiplier by Integer Linear Programming
  ☆13Updated 3 years ago