hkust-zhiyao / RTL-Coder
A new LLM solution for RTL code generation, achieving state-of-the-art performance in non-commercial solutions and outperforming GPT-3.5.
☆129Updated last month
Related projects ⓘ
Alternatives and complementary repositories for RTL-Coder
- An open-source benchmark for generating design RTL with natural language☆70Updated 2 weeks ago
- Verilog evaluation benchmark for large language model☆179Updated 3 months ago
- ☆119Updated last month
- ☆130Updated 4 months ago
- 🕹 OpenPARF: An Open-Source Placement and Routing Framework for Large-Scale Heterogeneous FPGAs with Deep Learning Toolkit☆116Updated last month
- A RISC-V BOOM Microarchitecture Power Modeling Framework☆19Updated last year
- ☆31Updated last month
- MasterRTL: A Pre-Synthesis PPA Estimation Framework for Any RTL Design☆35Updated 2 months ago
- OpenABC-D is a large-scale labeled dataset generated by synthesizing open source hardware IPs. This dataset can be used for various graph…☆115Updated last month
- ☆45Updated 2 months ago
- Research and Materials on Hardware implementation of Transformer Model☆211Updated 2 weeks ago
- The codes and artifacts associated with our MICRO'22 paper titled: "Adaptable Butterfly Accelerator for Attention-based NNs via Hardware …☆112Updated last year
- PANDA: Architecture-Level Power Evaluation by Unifying Analytical and Machine Learning Solutions☆14Updated 11 months ago
- Generating Hardware Verification Assertions from Design Specifications via Multi-LLMs☆20Updated 3 weeks ago
- Data is all you need: Finetuning LLMs for Chip Design via an Automated design-data augmentation framework (DAC 2024)☆21Updated 4 months ago
- FREE TPU V3plus for FPGA is the free version of a commercial AI processor (EEP-TPU) for Deep Learning EDGE Inference☆109Updated last year
- This repo awesome-AI4EDA contains the source for the webpage: https://ai4eda.github.io, which is a curated paper list of awesome AI for E…☆128Updated 5 months ago
- CGRA-Flow is an integrated framework for CGRA compilation, exploration, synthesis, and development.☆113Updated last week
- IC implementation of Systolic Array for TPU☆152Updated last month
- Edge-MoE: Memory-Efficient Multi-Task Vision Transformer Architecture with Task-level Sparsity via Mixture-of-Experts☆87Updated 6 months ago
- An FPGA Accelerator for Transformer Inference☆73Updated 2 years ago
- DATE'24 paper: "Hierarchical Source-to-Post-Route QoR Prediction in High-Level Synthesis with GNNs"☆13Updated last month
- AMF-Placer 2.0: An open-source timing-driven analytical mixed-size FPGA placer of heterogeneous resources (LUT/FF/LUTRAM/MUX/CARRY/DSP/BR…☆97Updated 8 months ago
- Dataset for ML-guided Accelerator Design☆31Updated this week
- mflowgen -- A Modular ASIC/FPGA Flow Generator☆233Updated last month
- ☆45Updated last month
- A SystemVerilog implementation of Row-Stationary dataflow and Hierarchical Mesh Network-on-Chip Architecture based on Eyeriss CNN Acceler…☆129Updated 4 years ago
- [HPCA'21] SpAtten: Efficient Sparse Attention Architecture with Cascade Token and Head Pruning☆76Updated 2 months ago
- ☆259Updated 3 years ago
- You can run it on pynq z1. The repository contains the relevant Verilog code, Vivado configuration and C code for sdk testing. The size o…☆118Updated 7 months ago