A new LLM solution for RTL code generation, achieving state-of-the-art performance in non-commercial solutions and outperforming GPT-3.5.
☆271Feb 9, 2025Updated last year
Alternatives and similar repositories for RTL-Coder
Users that are interested in RTL-Coder are comparing it to the libraries listed below. We may earn a commission when you buy through links labeled 'Ad' on this page.
Sorting:
- An open-source benchmark for generating design RTL with natural language☆178Nov 8, 2024Updated last year
- Verilog evaluation benchmark for large language model☆391Jul 14, 2025Updated 8 months ago
- Annotating Slack Directly on Your Verilog: Fine-Grained RTL Timing Evaluation for Early Optimization☆43May 29, 2025Updated 10 months ago
- SpecLLM: Exploring Generation and Review of VLSI Design Specification with Large Language Model☆16Jan 29, 2024Updated 2 years ago
- ☆199Oct 17, 2024Updated last year
- Wordpress hosting with auto-scaling on Cloudways • AdFully Managed hosting built for WordPress-powered businesses that need reliable, auto-scalable hosting. Cloudways SafeUpdates now available.
- MasterRTL: A Pre-Synthesis PPA Estimation Framework for Any RTL Design☆67May 29, 2025Updated 10 months ago
- PANDA: Architecture-Level Power Evaluation by Unifying Analytical and Machine Learning Solutions☆18Dec 18, 2023Updated 2 years ago
- CircuitFusion: Multimodal Circuit Representation Learning for Agile Chip Design (ICLR'25)☆34Apr 13, 2025Updated 11 months ago
- A circuit-element level explainer to explain machine learning model's prediction on chip layouts.☆18Oct 30, 2023Updated 2 years ago
- Generating Hardware Verification Assertions from Design Specifications via Multi-LLMs☆57Oct 28, 2024Updated last year
- ☆55Oct 8, 2024Updated last year
- Fix syntax errors of LLM-generated RTL☆45May 23, 2024Updated last year
- ☆45Mar 10, 2025Updated last year
- NetTAG: A Multimodal RTL-and-Layout-Aligned Netlist Foundation Model via Text-Attributed Graph (DAC'25)☆25Dec 21, 2025Updated 3 months ago
- NordVPN Special Discount Offer • AdSave on top-rated NordVPN 1 or 2-year plans with secure browsing, privacy protection, and support for for all major platforms.
- ☆270Jul 8, 2024Updated last year
- This is a repo to store circuit design datasets☆19Jan 17, 2024Updated 2 years ago
- [DATE 2025] haven: hallucination-mitigated llm for verilog code generation aligned with hdl engineers☆39Jul 9, 2025Updated 8 months ago
- OriGen: Enhancing RTL Code Generation with Code-to-Code Augmentation and Self-Reflection(ICCAD 2024)☆29Oct 20, 2024Updated last year
- ☆54Sep 4, 2025Updated 6 months ago
- LLM Evaluation Benchmark on Hardware Formal Verification☆41Apr 3, 2025Updated 11 months ago
- This is a python repo for flattening Verilog☆20Dec 19, 2025Updated 3 months ago
- ☆59Jan 19, 2026Updated 2 months ago
- OpenABC-D is a large-scale labeled dataset generated by synthesizing open source hardware IPs. This dataset can be used for various graph…☆145Jul 23, 2025Updated 8 months ago
- Wordpress hosting with auto-scaling on Cloudways • AdFully Managed hosting built for WordPress-powered businesses that need reliable, auto-scalable hosting. Cloudways SafeUpdates now available.
- Data is all you need: Finetuning LLMs for Chip Design via an Automated design-data augmentation framework (DAC 2024)☆60Dec 17, 2024Updated last year
- MAGE: A Multi-Agent Engine for Automated RTL Code Generation☆94Apr 11, 2025Updated 11 months ago
- LLM4HWDesign Starting Toolkit☆19Oct 4, 2024Updated last year
- DeepGate3 for ICCAD2024☆13May 26, 2025Updated 10 months ago
- ☆45May 18, 2024Updated last year
- This is the Github Repo for the paper: VeriReason: Reinforcement Learning with Testbench Feedback for Reasoning-Enhanced Verilog Generati…☆21Sep 25, 2025Updated 6 months ago
- AutoSVA is a tool to automatically generate formal testbenches for unit-level RTL verification. The goal is to, based on annotations made…☆99Mar 29, 2024Updated 2 years ago
- ☆141Mar 11, 2026Updated 2 weeks ago
- ☆28Jun 25, 2024Updated last year
- DigitalOcean Gradient AI Platform • AdBuild production-ready AI agents using customizable tools or access multiple LLMs through a single endpoint. Create custom knowledge bases or connect external data.
- [IJCAI 2024] QiMeng-CPU-v1: Automated CPU Design by Learning from Input-Output Examples☆27May 4, 2025Updated 10 months ago
- Hop-Wise Graph Attention for Scalable and Generalizable Learning on Circuits☆35Aug 25, 2024Updated last year
- ☆99Jun 24, 2025Updated 9 months ago
- PANDA: Architecture-Level Power Evaluation by Unifying Analytical and Machine Learning Solutions☆11Dec 18, 2023Updated 2 years ago
- Boosted E-Graph Extraction with Adaptive Heuristics and Exact Solving☆29Jan 7, 2026Updated 2 months ago
- LLMs and the Future of Chip Design: Unveiling Security Risks and Building Trust☆38May 17, 2024Updated last year
- Collection for submission (Hardware Model Checking Benchmark)☆13Nov 9, 2025Updated 4 months ago