A new LLM solution for RTL code generation, achieving state-of-the-art performance in non-commercial solutions and outperforming GPT-3.5.
☆330Feb 9, 2025Updated last year
Alternatives and similar repositories for RTL-Coder
Users that are interested in RTL-Coder are comparing it to the libraries listed below. We may earn a commission when you buy through links labeled 'Ad' on this page.
Sorting:
- An open-source benchmark for generating design RTL with natural language☆244Aug 15, 2026Updated 2 months ago
- Verilog evaluation benchmark for large language model☆492Jul 14, 2025Updated last year
- ☆211Oct 17, 2024Updated 2 years ago
- ☆58Oct 8, 2024Updated 2 years ago
- Annotating Slack Directly on Your Verilog: Fine-Grained RTL Timing Evaluation for Early Optimization☆54May 29, 2025Updated last year
- 1-Click AI Models by DigitalOcean Gradient • AdDeploy popular AI models on DigitalOcean Gradient GPU virtual machines with just a single click. Zero configuration with optimized deployments.
- MasterRTL: A Pre-Synthesis PPA Estimation Framework for Any RTL Design☆83May 29, 2025Updated last year
- CircuitFusion: Multimodal Circuit Representation Learning for Agile Chip Design (ICLR'25)☆46Apr 13, 2025Updated last year
- SpecLLM: Exploring Generation and Review of VLSI Design Specification with Large Language Model☆19Jan 29, 2024Updated 2 years ago
- Generating Hardware Verification Assertions from Design Specifications via Multi-LLMs☆72Oct 28, 2024Updated 2 years ago
- ☆13Jul 30, 2025Updated last year
- NetTAG: A Multimodal RTL-and-Layout-Aligned Netlist Foundation Model via Text-Attributed Graph (DAC'25)☆25May 20, 2026Updated 5 months ago
- Fix syntax errors of LLM-generated RTL☆60May 23, 2024Updated 2 years ago
- ☆64Mar 10, 2025Updated last year
- PANDA: Architecture-Level Power Evaluation by Unifying Analytical and Machine Learning Solutions☆19Dec 18, 2023Updated 2 years ago
- Deploy to Railway using AI coding agents - Free Credits Offer • AdUse Claude Code, Codex, OpenCode, and more. Autonomous software development now has the infrastructure to match with Railway.
- A circuit-element level explainer to explain machine learning model's prediction on chip layouts.☆18Oct 30, 2023Updated 3 years ago
- MAGE: A Multi-Agent Engine for Automated RTL Code Generation☆143Apr 11, 2025Updated last year
- ☆14Oct 13, 2025Updated last year
- OriGen: Enhancing RTL Code Generation with Code-to-Code Augmentation and Self-Reflection(ICCAD 2024)☆35Oct 20, 2024Updated 2 years ago
- ☆300Jul 8, 2024Updated 2 years ago
- This is the Github Repo for the paper: VeriReason: Reinforcement Learning with Testbench Feedback for Reasoning-Enhanced Verilog Generati…☆29Sep 25, 2025Updated last year
- RTL-Repo: A Benchmark for Evaluating LLMs on Large-Scale RTL Design Projects - IEEE LAD'24☆35Jun 5, 2024Updated 2 years ago
- This is a repo to store circuit design datasets☆19Jan 17, 2024Updated 2 years ago
- ☆252Jun 8, 2026Updated 4 months ago
- Deploy to Railway using AI coding agents - Free Credits Offer • AdUse Claude Code, Codex, OpenCode, and more. Autonomous software development now has the infrastructure to match with Railway.
- ☆50May 18, 2024Updated 2 years ago
- ☆65Sep 4, 2025Updated last year
- [DATE 2025] haven: hallucination-mitigated llm for verilog code generation aligned with hdl engineers☆44Jul 9, 2025Updated last year
- ChipSeek: Optimizing Verilog Generation via EDA-Integrated Reinforcement Learning (ACL 2026)☆17Aug 19, 2026Updated 2 months ago
- ☆191Mar 10, 2025Updated last year
- LLM Evaluation Benchmark on Hardware Formal Verification☆46Apr 3, 2025Updated last year
- Dr.RTL: Autonomous Agentic RTL optimization through Tool-Grounded Self-Improvement☆37Sep 4, 2026Updated 2 months ago
- ☆65Jul 13, 2026Updated 3 months ago
- This is the Github Repo for the paper: MCP4EDA: LLM-Powered Model Context Protocol RTL-to-GDSII Automation with Backend Aware Synthesis O…☆112Jul 29, 2025Updated last year
- Managed hosting for WordPress and PHP on Cloudways • AdManaged hosting for WordPress, Magento, Laravel, or PHP apps, on multiple cloud providers. Deploy in minutes on Cloudways by DigitalOcean.
- PRO-V: An Efficient Program Generation Multi-Agent System for Automatic RTL Verification☆36Dec 11, 2025Updated 10 months ago
- LLMs and the Future of Chip Design: Unveiling Security Risks and Building Trust☆42May 17, 2024Updated 2 years ago
- ☆22Oct 17, 2024Updated 2 years ago
- ☆59Jan 6, 2026Updated 10 months ago
- ICCD'24 paper: "AutoVCoder: A systematic framework for automated verilog code generation"☆27Dec 17, 2024Updated last year
- OpenABC-D is a large-scale labeled dataset generated by synthesizing open source hardware IPs. This dataset can be used for various graph…☆153Jul 23, 2025Updated last year
- ☆62Oct 10, 2026Updated 3 weeks ago