This github repository summarizes relevant papers for shift left techniques in electronic design automation (EDA).
☆36Jun 17, 2026Updated 3 months ago
Alternatives and similar repositories for Shift-Left-EDA-Papers
Users that are interested in Shift-Left-EDA-Papers are comparing it to the libraries listed below. We may earn a commission when you buy through links labeled 'Ad' on this page.
Sorting:
- Research paper based on or related to ABC.☆74Jun 11, 2026Updated 3 months ago
- E-morphic: Scalable Equality Saturation for Structural Exploration in Logic Synthesis (DAC2025)☆32Jun 23, 2025Updated last year
- Logic optimization and technology mapping tool.☆20Oct 12, 2023Updated 2 years ago
- A Lean-embedded framework to verify Verilog modules☆15Sep 21, 2026Updated last week
- An advanced circuit-based sat solver☆39Feb 24, 2025Updated last year
- AI Agents on DigitalOcean Gradient AI Platform • AdBuild production-ready AI agents using customizable tools or access multiple LLMs through a single endpoint. Create custom knowledge bases or connect external data.
- ☆13Jan 20, 2023Updated 3 years ago
- Annotating Slack Directly on Your Verilog: Fine-Grained RTL Timing Evaluation for Early Optimization☆49May 29, 2025Updated last year
- Collection for submission (Hardware Model Checking Benchmark)☆13Nov 9, 2025Updated 10 months ago
- MasterRTL: A Pre-Synthesis PPA Estimation Framework for Any RTL Design☆79May 29, 2025Updated last year
- ☆61Jan 19, 2026Updated 8 months ago
- This is a repo to store circuit design datasets☆19Jan 17, 2024Updated 2 years ago
- Taiwei-3D-Flow☆64Sep 10, 2026Updated 2 weeks ago
- GPU-based logic synthesis tool☆111Mar 31, 2026Updated 5 months ago
- Semi-Tenser Product based SAT and AllSAT solver, where it can solve CNF and circuit input.☆17Aug 2, 2023Updated 3 years ago
- 1-Click AI Models by DigitalOcean Gradient • AdDeploy popular AI models on DigitalOcean Gradient GPU virtual machines with just a single click. Zero configuration with optimized deployments.
- Official implementation of paper "Open3DBench: Open-Source Benchmark for 3D-IC Backend Implementation and PPA Evaluation".☆160Sep 15, 2026Updated last week
- ☆30Jun 25, 2024Updated 2 years ago
- Open-source, agent-agnostic RTL formal verification skill library for AI coding agents: JasperGold FPV, SVA, proof optimization, and TCL …☆34Jul 27, 2026Updated 2 months ago
- Collection of digital hardware modules & projects (benchmarks)☆111Feb 27, 2026Updated 7 months ago
- Artificial Netlist Generator☆48Mar 19, 2024Updated 2 years ago
- Tools for manipulating CHC and related files☆15Apr 21, 2023Updated 3 years ago
- C++ header-only exact synthesis library☆19Jan 18, 2023Updated 3 years ago
- ☆25May 8, 2025Updated last year
- A framework for building hardware verification platform using software method☆40Apr 19, 2026Updated 5 months ago
- Wordpress hosting with auto-scaling - Free Trial Offer • AdFully Managed hosting for WordPress and WooCommerce businesses that need reliable, auto-scalable performance. Cloudways SafeUpdates now available.
- MapTune: Advancing ASIC Technology Mapping via Reinforcement Learning Guided Library Tuning Mingju Liu, Daniel Robinson, Yingjie Li, Cunx…☆30Apr 9, 2025Updated last year
- Contract-Aware RTL Code Generation Agents with Temporal Tracing, Slicing and Formal Verification☆26Jan 28, 2026Updated 8 months ago
- ☆20Dec 29, 2014Updated 11 years ago
- OpenROAD's Chatbot Assistant☆47Updated this week
- ☆21Oct 27, 2022Updated 3 years ago
- LLM Evaluation Benchmark on Hardware Formal Verification☆44Apr 3, 2025Updated last year
- Datasets for EDA LLM research☆46Jan 17, 2025Updated last year
- Automatic generation of architecture-level models for hardware from its RTL design.☆16Apr 12, 2023Updated 3 years ago
- Open stadard cell library for open 28nm process☆18Jul 5, 2023Updated 3 years ago
- Deploy on Railway without the complexity - Free Credits Offer • AdConnect your repo and Railway handles the rest with instant previews. Quickly provision container image services, databases, and storage volumes.
- A collection of datapath circuit design and verification benchmarks☆19Aug 24, 2026Updated last month
- ☆18Jun 12, 2026Updated 3 months ago
- ☆50May 18, 2024Updated 2 years ago
- ☆10Nov 19, 2015Updated 10 years ago
- A fork of the Kissat SAT solver with additional features. Supports incremental solving.☆17Aug 13, 2022Updated 4 years ago
- A tool for synthesizing Verilog programs☆123Aug 25, 2025Updated last year
- ☆14Aug 27, 2020Updated 6 years ago