Alternatives and similar repositories for GL0AM

Users that are interested in GL0AM are comparing it to the libraries listed below

• dian-lun-lin / RTLflow
  A GPU acceleration flow for RTL simulation with batch stimulus
  ☆113Updated last year
• StanfordAHA / lake
  Lake is a framework for generating synthesizable memory modules from a high-level behavioral specification and widely-available memory ma…
  ☆22Updated this week
• pulp-platform / ELAU
  ☆19Updated last year
• pku-liang / Cement
  The Next-gen Language & Compiler Powering Efficient Hardware Design
  ☆29Updated 6 months ago
• pku-liang / ksim
  ☆44Updated 6 months ago
• zslwyuan / Light-HLS
  Fast, Accurate and Convenient Light-Weight HLS Framework for Academic Design Space Exploration and Evaluation. (LLVM-11)
  ☆60Updated 3 years ago
• Yu-Maryland / Verilog-to-PyG
  ☆24Updated last year
• epfl-vlsc / parendi
  Parendi: Thousand-way Parallel RTL Simulation on the Graphcore IPU
  ☆23Updated last year
• scale-lab / BLASYS
  An Approximate Logic Synthesis Framework based on Boolean Matrix Factorization
  ☆31Updated last year
• pku-dasys / cocoon
  An infrastructure for integrated EDA
  ☆41Updated 2 years ago
• circt-hls / circt-hls
  CIRCT-based HLS compilation flows, debugging, and cosimulation tools.
  ☆50Updated 2 years ago
• YosysHQ / eqy
  Equivalence checking with Yosys
  ☆45Updated this week
• Xilinx / fpga24_routing_contest
  Runtime-First FPGA Interchange Routing Contest @ FPGA’24
  ☆33Updated 2 months ago
• jianyicheng / DSS
  DASS HLS Compiler
  ☆29Updated last year
• bespoke-silicon-group / bsg_bladerunner
  Meta-Repository for Bespoke Silicon Group's Manycore Architecture (A.K.A HammerBlade)
  ☆41Updated last month
• HKUSTGZ-MICS-LYU / FlattenRTL
  This is a python repo for flattening Verilog
  ☆18Updated 2 months ago
• ekiwi / rtl-repair
  Fast Symbolic Repair of Hardware Design Code
  ☆25Updated 6 months ago
• Intuity / nexus
  Open source RTL simulation acceleration on commodity hardware
  ☆28Updated 2 years ago
• cornell-zhang / HOGA
  Hop-Wise Graph Attention for Scalable and Generalizable Learning on Circuits
  ☆30Updated 11 months ago
• IntelLabs / FloorSet
  ☆74Updated last month
• jianyicheng / iiProver
  An LLVM pass to prove that an II works for the given loop for Vitis HLS
  ☆11Updated 3 years ago
• rahulk29 / sram22
  A configurable SRAM generator
  ☆53Updated 3 weeks ago
• UCLA-VAST / GNN-DSE
  DAC'22 paper: "Automated Accelerator Optimization Aided by Graph Neural Networks"
  ☆40Updated last year
• rachelselinar / DREAMPlaceFPGA
  An Open-Source Analytical Placer for Large Scale Heterogeneous FPGAs using Deep-Learning Toolkit
  ☆82Updated 3 months ago
• JBlocklove / LLMs-for-EDA-Tutorial
  ☆52Updated 2 months ago
• StanfordAHA / garnet
  Next generation CGRA generator
  ☆112Updated this week
• wincle626 / HLS_Legup
  ☆27Updated 7 years ago
• SJTU-ECTL / GOMIL
  GOMIL: Global Optimization of Multiplier by Integer Linear Programming
  ☆13Updated 3 years ago
• broccolimicro / loom
  design and verification of asynchronous circuits
  ☆39Updated 2 weeks ago
• icgrp / hipr
  ☆15Updated 2 years ago