Alternatives and similar repositories for GL0AM

Users that are interested in GL0AM are comparing it to the libraries listed below

• StanfordAHA / lake
  Lake is a framework for generating synthesizable memory modules from a high-level behavioral specification and widely-available memory ma…
  ☆22Updated last month
• YosysHQ / eqy
  Equivalence checking with Yosys
  ☆45Updated last week
• dian-lun-lin / RTLflow
  A GPU acceleration flow for RTL simulation with batch stimulus
  ☆112Updated last year
• pku-liang / Cement
  The Next-gen Language & Compiler Powering Efficient Hardware Design
  ☆29Updated 6 months ago
• scale-lab / BLASYS
  An Approximate Logic Synthesis Framework based on Boolean Matrix Factorization
  ☆31Updated last year
• epfl-vlsc / parendi
  Parendi: Thousand-way Parallel RTL Simulation on the Graphcore IPU
  ☆22Updated last year
• Xilinx / fpga24_routing_contest
  Runtime-First FPGA Interchange Routing Contest @ FPGA’24
  ☆33Updated last month
• circt-hls / circt-hls
  CIRCT-based HLS compilation flows, debugging, and cosimulation tools.
  ☆49Updated 2 years ago
• zslwyuan / Light-HLS
  Fast, Accurate and Convenient Light-Weight HLS Framework for Academic Design Space Exploration and Evaluation. (LLVM-11)
  ☆60Updated 3 years ago
• jianyicheng / DSS
  DASS HLS Compiler
  ☆29Updated last year
• yzwangfeng / reram-synthesis
  A synthesis flow for hybrid processing-in-RRAM modes
  ☆12Updated 4 years ago
• UCLA-VAST / heterohalide
  HeteroHalide: From Image Processing DSL to Efficient FPGA Acceleration
  ☆15Updated 4 years ago
• pku-dasys / cocoon
  An infrastructure for integrated EDA
  ☆41Updated last year
• StanfordAHA / lassen
  The PE for the second generation CGRA (garnet).
  ☆17Updated 2 months ago
• ekiwi / rtl-repair
  Fast Symbolic Repair of Hardware Design Code
  ☆25Updated 5 months ago
• pulp-platform / ELAU
  ☆19Updated last year
• broccolimicro / loom
  design and verification of asynchronous circuits
  ☆39Updated last week
• bespoke-silicon-group / bsg_bladerunner
  Meta-Repository for Bespoke Silicon Group's Manycore Architecture (A.K.A HammerBlade)
  ☆41Updated last month
• SJTU-ECTL / GOMIL
  GOMIL: Global Optimization of Multiplier by Integer Linear Programming
  ☆13Updated 3 years ago
• wincle626 / HLS_Legup
  ☆27Updated 7 years ago
• The-OpenROAD-Project / TritonCTS
  Source codes and calibration scripts for clock tree synthesis
  ☆40Updated 5 years ago
• spcl / apfp
  FPGA acceleration of arbitrary precision floating point computations.
  ☆40Updated 3 years ago
• ehw-fit / ariths-gen
  Generator of arithmetic circuits (multipliers, adders) and approximate circuits
  ☆35Updated 5 months ago
• Kuree / cgra_pnr
  Fast PnR toolchain for CGRA
  ☆18Updated 11 months ago
• sfu-arch / muir
  ☆24Updated 4 years ago
• NVlabs / iccad2020-GPUgatesim
  ☆14Updated 4 years ago
• icgrp / hipr
  ☆15Updated 2 years ago
• jianyicheng / iiProver
  An LLVM pass to prove that an II works for the given loop for Vitis HLS
  ☆11Updated 3 years ago
• ucb-bar / RoSE
  A unified simulation platform that combines hardware and software, enabling pre-silicon, full-stack, closed-loop evaluation of your robot…
  ☆43Updated 3 months ago
• daitoto / EDA-wiki
  EDA wiki
  ☆54Updated 2 years ago