amahzoon / genmulLinks
☆17Updated 4 years ago
Alternatives and similar repositories for genmul
Users that are interested in genmul are comparing it to the libraries listed below
Sorting:
- GOMIL: Global Optimization of Multiplier by Integer Linear Programming☆13Updated 4 years ago
- E-Syn: E-Graph Rewriting with Technology-Aware Cost Functions for Logic Synthesis (DAC 2024)☆36Updated last year
- Logic optimization and technology mapping tool.☆19Updated last year
- Research paper based on or related to ABC.☆52Updated 2 months ago
- ☆19Updated 2 years ago
- Generator of arithmetic circuits (multipliers, adders) and approximate circuits☆36Updated last month
- Generating Hardware Verification Assertions from Design Specifications via Multi-LLMs☆38Updated 11 months ago
- This is a python repo for flattening Verilog☆19Updated 4 months ago
- ☆23Updated 3 weeks ago
- MapTune: Advancing ASIC Technology Mapping via Reinforcement Learning Guided Library Tuning Mingju Liu, Daniel Robinson, Yingjie Li, Cunx…☆22Updated 5 months ago
- AMulet 2. - A better AIG Multiplier Examination Tool☆26Updated 2 years ago
- ☆12Updated 2 years ago
- ☆25Updated last year
- Gamora: Graph Learning based Symbolic Reasoning for Large-Scale Boolean Networks (DAC'23)☆50Updated 8 months ago
- Collection of digital hardware modules & projects (benchmarks)☆62Updated 3 weeks ago
- EPFL and ISCAS85 combinational benchmark circuits in generic gate verilog☆28Updated 5 years ago
- MasterRTL: A Pre-Synthesis PPA Estimation Framework for Any RTL Design☆55Updated 4 months ago
- GPU-based logic synthesis tool☆90Updated last month
- Benchmarks for Approximate Circuit Synthesis☆17Updated 5 years ago
- A high-efficiency hybrid solving CEC algorithm☆13Updated 2 years ago
- ALSRAC: Approximate Logic Synthesis by Resubstitution with Approximate Care Set☆19Updated 9 months ago
- Fast Symbolic Repair of Hardware Design Code☆26Updated 8 months ago
- A logic synthesis tool☆81Updated 3 weeks ago
- ☆38Updated last year
- Collection for submission (Hardware Model Checking Benchmark)☆10Updated 11 months ago
- Awesome machine learning for logic synthesis☆29Updated 3 years ago
- ☆23Updated last year
- The release for paper "Scalable and Effective Arithmetic Tree Generation for Adder and Multiplier Designs"☆14Updated last year
- A Logic Synthesis tool based on "Mockturtle: EPFL Logic Synthesis Library " and "ABC: System for Sequential Logic Synthesis and Formal Ve…☆34Updated 2 months ago
- LLM Evaluation Benchmark on Hardware Formal Verification☆30Updated 6 months ago