Alternatives and similar repositories for genmul

Users that are interested in genmul are comparing it to the libraries listed below

• OSCC-Project / iMap
  Logic optimization and technology mapping tool.
  ☆20Updated 2 years ago
• Gy-Hu / E-Syn
  E-Syn: E-Graph Rewriting with Technology-Aware Cost Functions for Logic Synthesis (DAC 2024)
  ☆41Updated last year
• SJTU-ECTL / GOMIL
  GOMIL: Global Optimization of Multiplier by Integer Linear Programming
  ☆13Updated 4 years ago
• ehw-fit / ariths-gen
  Generator of arithmetic circuits (multipliers, adders) and approximate circuits
  ☆39Updated 5 months ago
• hkustgz-zhang-lab / ABCPaperCheck
  Research paper based on or related to ABC.
  ☆70Updated 2 weeks ago
• Yu-Maryland / MapTune
  MapTune: Advancing ASIC Technology Mapping via Reinforcement Learning Guided Library Tuning Mingju Liu, Daniel Robinson, Yingjie Li, Cunx…
  ☆22Updated 9 months ago
• Yu-Maryland / Gamora
  Gamora: Graph Learning based Symbolic Reasoning for Large-Scale Boolean Networks (DAC'23)
  ☆55Updated last year
• HKUSTGZ-MICS-LYU / FlattenRTL
  This is a python repo for flattening Verilog
  ☆20Updated last month
• SJTU-ECTL / ALSRAC
  ALSRAC: Approximate Logic Synthesis by Resubstitution with Approximate Care Set
  ☆21Updated last year
• Entropy-xcy / sns
  ☆20Updated 3 years ago
• Yu-Maryland / Verilog-to-PyG
  ☆30Updated last year
• nbulsi / also
  A logic synthesis tool
  ☆85Updated 4 months ago
• jpsety / verilog_benchmark_circuits
  EPFL and ISCAS85 combinational benchmark circuits in generic gate verilog
  ☆29Updated 6 years ago
• ekiwi / rtl-repair
  Fast Symbolic Repair of Hardware Design Code
  ☆33Updated last year
• ispras / hdl-benchmarks
  Collection of digital hardware modules & projects (benchmarks)
  ☆79Updated last month
• fangwenji / tacas23-wasim
  ☆13Updated 3 years ago
• HybridCEC / Hybrid-CEC
  A high-efficiency hybrid solving CEC algorithm
  ☆14Updated 2 years ago
• d-kfmnn / amulet2
  AMulet 2. - A better AIG Multiplier Examination Tool
  ☆26Updated last month
• hkust-zhiyao / AssertLLM
  Generating Hardware Verification Assertions from Design Specifications via Multi-LLMs
  ☆49Updated last year
• sterin / super-prove-build
  ☆14Updated 5 years ago
• cornell-zhang / eqmap
  Using e-graphs for logic synthesis (ICCAD'25)
  ☆31Updated this week
• cuhk-eda / CULS
  GPU-based logic synthesis tool
  ☆97Updated 2 months ago
• hkust-zhiyao / MasterRTL
  MasterRTL: A Pre-Synthesis PPA Estimation Framework for Any RTL Design
  ☆66Updated 8 months ago
• HKUST-GZ-VLSI / Design-Dataset
  This is a repo to store circuit design datasets
  ☆19Updated 2 years ago
• PrincetonUniversity / IMDb-Archive
  ILA Model Database
  ☆24Updated 5 years ago
• zshi0616 / python-deepgate
  ☆27Updated last year
• NVlabs / FVEval
  LLM Evaluation Benchmark on Hardware Formal Verification
  ☆35Updated 10 months ago
• scale-lab / BACS
  Benchmarks for Approximate Circuit Synthesis
  ☆17Updated 5 years ago
• zslwyuan / AutoCellLibX
  AutoCellLibX: Automated Standard Cell Library Extension Based on Pattern Mining
  ☆18Updated 3 years ago
• panhomyoung / phyLS
  A Logic Synthesis tool based on "Mockturtle: EPFL Logic Synthesis Library " and "ABC: System for Sequential Logic Synthesis and Formal Ve…
  ☆39Updated last month