hkust-zhiyao / PANDA

Related projects ⓘ

Alternatives and complementary repositories for PANDA

• zhaijw18 / mcpat-calib-public
  A RISC-V BOOM Microarchitecture Power Modeling Framework
  ☆19Updated last year
• baichen318 / boom-explorer-public
  The open-sourced version of BOOM-Explorer
  ☆32Updated last year
• ecolab-nus / morpher-v2
  An Open-Source Tool for CGRA Accelerators
  ☆17Updated 7 months ago
• UT-LCA / ML4Accel-Dataset
  Dataset for ML-guided Accelerator Design
  ☆31Updated this week
• hkust-zhiyao / MasterRTL
  MasterRTL: A Pre-Synthesis PPA Estimation Framework for Any RTL Design
  ☆35Updated 2 months ago
• ecolab-nus / morpher
  An Open-Source Tool for CGRA Accelerators
  ☆57Updated 3 months ago
• pku-dasys / pillars
  An integrated CGRA design framework
  ☆83Updated last week
• yhqiu16 / TRAM
  Template-based Reconfigurable Architecture Modeling Framework
  ☆13Updated 2 years ago
• diwu1990 / uSystolic-Sim
  A systolic array simulator for multi-cycle MACs and varying-byte words, with the paper accepted to HPCA 2022.
  ☆65Updated 3 years ago
• pnnl / soda-opt
  ☆37Updated 4 months ago
• FCAS-LAB / chiplet_simulators
  A list of our chiplet simulaters
  ☆21Updated 3 years ago
• sjtu-zhao-lab / hierarchical-gnn-for-hls
  DATE'24 paper: "Hierarchical Source-to-Post-Route QoR Prediction in High-Level Synthesis with GNNs"
  ☆13Updated last month
• tancheng / CGRA-Mapper
  An LLVM pass that can generate CDFG and map the target loops onto a parameterizable CGRA.
  ☆56Updated last month
• hkust-zhiyao / RTL-Timer
  Annotating Slack Directly on Your Verilog: Fine-Grained RTL Timing Evaluation for Early Optimization
  ☆17Updated 4 months ago
• baichen318 / arch-explorer
  ArchExplorer: Microarchitecture Exploration Via Bottleneck Analysis
  ☆30Updated 9 months ago
• pku-dasys / easymac
  ☆15Updated 2 years ago
• hkust-zhiyao / APPLE
  A circuit-element level explainer to explain machine learning model's prediction on chip layouts.
  ☆17Updated last year
• hkust-zhiyao / RTLLM
  An open-source benchmark for generating design RTL with natural language
  ☆70Updated 2 weeks ago
• UIUC-ChenLab / ScaleHLS-HIDA
  ☆37Updated 8 months ago
• tancheng / CGRA-Flow
  CGRA-Flow is an integrated framework for CGRA compilation, exploration, synthesis, and development.
  ☆113Updated last week
• ABKGroup / TritonPart
  The first version of TritonPart
  ☆22Updated 10 months ago
• zlinaf / PowerGear
  [DATE 2022] PowerGear: Early-Stage Power Estimation in FPGA HLS via Heterogeneous Edge-Centric GNNs
  ☆17Updated 2 years ago
• SFU-HiAccel / HiSpMV
  [FPGA 2024]FPGA Accelerator for Imbalanced SpMV using HLS
  ☆7Updated last month
• tancheng / mlir-cgra
  An MLIR dialect to enable the efficient acceleration of ML model on CGRAs.
  ☆53Updated last month
• lydiawunan / HLS-Perf-Prediction-with-GNNs
  High-Level Synthesis Performance Prediction using GNNs: Benchmarking, Modeling, and Advancing
  ☆45Updated 5 months ago
• Yinxiao-Feng / chiplet-network-sim
  ☆13Updated 3 weeks ago
• sharc-lab / gnn-builder
  An Automated Framework for Generic Graph Neural Network Accelerator Generation, Simulation, and Optimization
  ☆19Updated last week
• andrewboutros / rad-flow
  The RAD flow is an open-source academic architecture exploration and evaluation flow for novel beyond-FPGA reconfigurable acceleration de…
  ☆30Updated this week
• rachelselinar / DREAMPlaceFPGA
  An Open-Source Analytical Placer for Large Scale Heterogeneous FPGAs using Deep-Learning Toolkit
  ☆75Updated 3 weeks ago
• sharc-lab / FlowGNN
  A dataflow architecture for universal graph neural network inference via multi-queue streaming.
  ☆68Updated last year