hkust-zhiyao / PANDA
PANDA: Architecture-Level Power Evaluation by Unifying Analytical and Machine Learning Solutions
☆15Updated last year
Alternatives and similar repositories for PANDA:
Users that are interested in PANDA are comparing it to the libraries listed below
- MasterRTL: A Pre-Synthesis PPA Estimation Framework for Any RTL Design☆46Updated 7 months ago
- The open-sourced version of BOOM-Explorer☆39Updated last year
- A RISC-V BOOM Microarchitecture Power Modeling Framework☆24Updated last year
- An integrated CGRA design framework☆88Updated last month
- Dataset for ML-guided Accelerator Design☆36Updated 5 months ago
- Template-based Reconfigurable Architecture Modeling Framework☆14Updated 2 years ago
- An Open-Source Tool for CGRA Accelerators☆64Updated 2 weeks ago
- A list of our chiplet simulaters☆32Updated last month
- ☆29Updated 4 months ago
- An Open-Source Tool for CGRA Accelerators☆21Updated last year
- ☆50Updated last month
- An MLIR dialect to enable the efficient acceleration of ML model on CGRAs.☆58Updated 6 months ago
- Generating Hardware Verification Assertions from Design Specifications via Multi-LLMs☆27Updated 6 months ago
- High-Level Synthesis Performance Prediction using GNNs: Benchmarking, Modeling, and Advancing☆50Updated 11 months ago
- Simulator framework for analysis of performance, energy consumption, area and cost of multi-node multi-chiplet tile-based manycore design…☆64Updated 10 months ago
- ☆16Updated 3 years ago
- This is a python repo for flattening Verilog☆16Updated 3 weeks ago
- [DATE 2022] PowerGear: Early-Stage Power Estimation in FPGA HLS via Heterogeneous Edge-Centric GNNs☆17Updated 3 years ago
- ☆22Updated 10 months ago
- An Automated Framework for Generic Graph Neural Network Accelerator Generation, Simulation, and Optimization☆21Updated 5 months ago
- ☆44Updated last month
- DATE'24 paper: "Hierarchical Source-to-Post-Route QoR Prediction in High-Level Synthesis with GNNs"☆17Updated 4 months ago
- ☆10Updated 2 years ago
- Collection of digital hardware modules & projects (benchmarks)☆55Updated this week
- A systolic array simulator for multi-cycle MACs and varying-byte words, with the paper accepted to HPCA 2022.☆76Updated 3 years ago
- A fast, accurate trace-based simulator for High-Level Synthesis.☆44Updated last month
- DRA+RISC-V Exploration Framework☆16Updated last year
- A comprehensive tool that allows for system-level performance estimation of chiplet-based In-Memory computing (IMC) architectures.☆21Updated 10 months ago
- Gamora: Graph Learning based Symbolic Reasoning for Large-Scale Boolean Networks (DAC'23)☆50Updated 3 months ago
- ArchExplorer: Microarchitecture Exploration Via Bottleneck Analysis☆31Updated last year