hkust-zhiyao / PANDALinks
PANDA: Architecture-Level Power Evaluation by Unifying Analytical and Machine Learning Solutions
☆16Updated last year
Alternatives and similar repositories for PANDA
Users that are interested in PANDA are comparing it to the libraries listed below
Sorting:
- A RISC-V BOOM Microarchitecture Power Modeling Framework☆24Updated 2 years ago
- MasterRTL: A Pre-Synthesis PPA Estimation Framework for Any RTL Design☆48Updated last week
- ☆32Updated this week
- A list of our chiplet simulaters☆32Updated 2 months ago
- The open-sourced version of BOOM-Explorer☆40Updated 2 years ago
- Simulator framework for analysis of performance, energy consumption, area and cost of multi-node multi-chiplet tile-based manycore design…☆68Updated 11 months ago
- An integrated CGRA design framework☆89Updated 2 months ago
- Dataset for ML-guided Accelerator Design☆37Updated 6 months ago
- ☆53Updated 2 months ago
- An Open-Source Tool for CGRA Accelerators☆65Updated last month
- Template-based Reconfigurable Architecture Modeling Framework☆14Updated 2 years ago
- ☆29Updated 7 months ago
- ArchExplorer: Microarchitecture Exploration Via Bottleneck Analysis☆31Updated last year
- A systolic array simulator for multi-cycle MACs and varying-byte words, with the paper accepted to HPCA 2022.☆77Updated 3 years ago
- An MLIR dialect to enable the efficient acceleration of ML model on CGRAs.☆59Updated 7 months ago
- ☆44Updated this week
- [DATE 2022] PowerGear: Early-Stage Power Estimation in FPGA HLS via Heterogeneous Edge-Centric GNNs☆17Updated 3 years ago
- HISIM introduces a suite of analytical models at the system level to speed up performance prediction for AI models, covering logic-on-log…☆36Updated 2 months ago
- An Open-Source Tool for CGRA Accelerators☆21Updated last year
- A Reconfigurable Accelerator with Data Reordering Support for Low-Cost On-Chip Dataflow Switching☆53Updated 2 months ago
- ☆16Updated 3 years ago
- ☆15Updated 2 years ago
- ACM TODAES Best Paper Award, 2022☆25Updated last year
- gem5 repository to study chiplet-based systems☆74Updated 6 years ago
- A portable framework to map DFG (dataflow graph, representing an application) on spatial accelerators.☆36Updated 2 years ago
- ☆10Updated 2 years ago
- ☆13Updated last year
- An end-to-end GCN inference accelerator written in HLS☆19Updated 3 years ago
- DATE'24 paper: "Hierarchical Source-to-Post-Route QoR Prediction in High-Level Synthesis with GNNs"☆17Updated 5 months ago
- Multi-core HW accelerator mapping optimization framework for layer-fused ML workloads.☆53Updated last month