Alternatives and similar repositories for PANDA

Users that are interested in PANDA are comparing it to the libraries listed below

• pku-dasys / pillars
  An integrated CGRA design framework
  ☆91Updated 8 months ago
• zhaijw18 / mcpat-calib-public
  A RISC-V BOOM Microarchitecture Power Modeling Framework
  ☆30Updated 2 years ago
• yhqiu16 / TRAM
  Template-based Reconfigurable Architecture Modeling Framework
  ☆14Updated 3 years ago
• baichen318 / boom-explorer-public
  The open-sourced version of BOOM-Explorer
  ☆45Updated 2 years ago
• UIUC-ChenLab / ScaleHLS-HIDA
  ☆61Updated 8 months ago
• PrincetonUniversity / muchiSim
  Simulator framework for analysis of performance, energy consumption, area and cost of multi-node multi-chiplet tile-based manycore design…
  ☆72Updated last year
• ecolab-nus / morpher-v2
  An Open-Source Tool for CGRA Accelerators
  ☆25Updated 2 months ago
• FCAS-LAB / chiplet_simulators
  A list of our chiplet simulaters
  ☆44Updated 5 months ago
• ecolab-nus / morpher
  An Open-Source Tool for CGRA Accelerators
  ☆76Updated 3 months ago
• Yinxiao-Feng / chiplet-network-sim
  ☆49Updated 6 months ago
• UT-LCA / ML4Accel-Dataset
  Dataset for ML-guided Accelerator Design
  ☆42Updated last year
• tancheng / CGRA-Flow
  CGRA-Flow is an integrated framework for CGRA compilation, exploration, synthesis, and development.
  ☆148Updated last week
• diwu1990 / uSystolic-Sim
  A systolic array simulator for multi-cycle MACs and varying-byte words, with the paper accepted to HPCA 2022.
  ☆83Updated 4 years ago
• hkust-zhiyao / MasterRTL
  MasterRTL: A Pre-Synthesis PPA Estimation Framework for Any RTL Design
  ☆59Updated 6 months ago
• cornell-zhang / HiSparse
  High-Performance Sparse Linear Algebra on HBM-Equipped FPGAs Using HLS
  ☆95Updated last year
• scalesim-project / scale-sim-v3
  ☆50Updated last week
• sharc-lab / LightningSim
  A fast, accurate trace-based simulator for High-Level Synthesis.
  ☆72Updated 8 months ago
• tancheng / mlir-cgra
  An MLIR dialect to enable the efficient acceleration of ML model on CGRAs.
  ☆64Updated last year
• maeri-project / MAERI_bsv
  MAERI: A DNN accelerator with reconfigurable interconnects to support flexible dataflow (http://synergy.ece.gatech.edu/tools/maeri/)
  ☆65Updated 4 years ago
• sharc-lab / FlowGNN
  A dataflow architecture for universal graph neural network inference via multi-queue streaming.
  ☆74Updated 2 years ago
• UCLA-VAST / tapa
  TAPA compiles task-parallel HLS program into high-performance FPGA accelerators. UCLA-maintained.
  ☆176Updated 3 months ago
• maeri-project / FEATHER
  A Reconfigurable Accelerator with Data Reordering Support for Low-Cost On-Chip Dataflow Switching
  ☆71Updated last month
• georgia-tech-synergy-lab / SIGMA
  RTL implementation of Flex-DPE.
  ☆115Updated 5 years ago
• linghaosong / Sextans
  An FPGA accelerator for general-purpose Sparse-Matrix Dense-Matrix Multiplication (SpMM).
  ☆91Updated last year
• MPSLab-ASU / ccf
  CGRA Compilation Framework
  ☆88Updated 2 years ago
• actlab-genesys / GeneSys
  An open-source parameterizable NPU generator with full-stack multi-target compilation stack for intelligent workloads.
  ☆69Updated 2 months ago
• SET-Scheduling-Project / GEMINI-HPCA2024
  Open-source Framework for HPCA2024 paper: Gemini: Mapping and Architecture Co-exploration for Large-scale DNN Chiplet Accelerators
  ☆105Updated 7 months ago
• PolyArch / dsa-framework
  Release of stream-specialization software/hardware stack.
  ☆119Updated 2 years ago
• UCLA-VAST / Stream-HLS
  An MLIR Complier for PyTorch/C/C++ Codes into HLS Dataflow Designs
  ☆55Updated 4 months ago
• synergy-noc-generators / Proteus
  ☆10Updated 2 years ago