hkust-zhiyao / RTLLM
An open-source benchmark for generating design RTL with natural language
☆77Updated 2 months ago
Alternatives and similar repositories for RTLLM:
Users that are interested in RTLLM are comparing it to the libraries listed below
- MasterRTL: A Pre-Synthesis PPA Estimation Framework for Any RTL Design☆39Updated 4 months ago
- A new LLM solution for RTL code generation, achieving state-of-the-art performance in non-commercial solutions and outperforming GPT-3.5.☆142Updated 3 months ago
- Verilog evaluation benchmark for large language model☆203Updated 4 months ago
- ☆125Updated 3 months ago
- PANDA: Architecture-Level Power Evaluation by Unifying Analytical and Machine Learning Solutions☆14Updated last year
- Generating Hardware Verification Assertions from Design Specifications via Multi-LLMs☆20Updated 2 months ago
- A circuit-element level explainer to explain machine learning model's prediction on chip layouts.☆17Updated last year
- A RISC-V BOOM Microarchitecture Power Modeling Framework☆23Updated last year
- This is a python repo for flattening Verilog☆15Updated last week
- ☆21Updated 6 months ago
- Dataset for ML-guided Accelerator Design☆33Updated 2 months ago
- Gamora: Graph Learning based Symbolic Reasoning for Large-Scale Boolean Networks (DAC'23)☆48Updated last week
- DATE'24 paper: "Hierarchical Source-to-Post-Route QoR Prediction in High-Level Synthesis with GNNs"☆13Updated last month
- ☆18Updated 2 months ago
- ☆145Updated 6 months ago
- The open-sourced version of BOOM-Explorer☆36Updated last year
- DAC'22 paper: "Automated Accelerator Optimization Aided by Graph Neural Networks"☆40Updated last year
- An integrated CGRA design framework☆85Updated 2 months ago
- Data is all you need: Finetuning LLMs for Chip Design via an Automated design-data augmentation framework (DAC 2024)☆30Updated last month
- Annotating Slack Directly on Your Verilog: Fine-Grained RTL Timing Evaluation for Early Optimization☆21Updated 6 months ago
- ☆37Updated 6 months ago
- An Open-Source Tool for CGRA Accelerators☆18Updated 8 months ago
- An Open-Source Tool for CGRA Accelerators☆58Updated last week
- A toolchain for rapid design space exploration of chiplet architectures☆41Updated 8 months ago
- ☆11Updated 4 months ago
- ☆35Updated 3 months ago
- ☆46Updated 3 months ago
- ☆26Updated 8 months ago
- A collection of ISCAS,ITC,TAU and other Benchmark Circuits for EDA tool evaluation.☆39Updated this week
- OpenABC-D is a large-scale labeled dataset generated by synthesizing open source hardware IPs. This dataset can be used for various graph…☆120Updated 3 months ago