UT-LCA / ML4Accel-DatasetLinks
Dataset for ML-guided Accelerator Design
☆39Updated 11 months ago
Alternatives and similar repositories for ML4Accel-Dataset
Users that are interested in ML4Accel-Dataset are comparing it to the libraries listed below
Sorting:
- [DATE 2022] PowerGear: Early-Stage Power Estimation in FPGA HLS via Heterogeneous Edge-Centric GNNs☆18Updated 3 years ago
- High-Level Synthesis Performance Prediction using GNNs: Benchmarking, Modeling, and Advancing☆51Updated last year
- MasterRTL: A Pre-Synthesis PPA Estimation Framework for Any RTL Design☆58Updated 4 months ago
- An integrated CGRA design framework☆91Updated 7 months ago
- A fast, accurate trace-based simulator for High-Level Synthesis.☆70Updated 6 months ago
- The open-sourced version of BOOM-Explorer☆43Updated 2 years ago
- ☆63Updated 5 months ago
- The RAD flow is an open-source academic architecture exploration and evaluation flow for novel beyond-FPGA reconfigurable acceleration de…☆38Updated 3 months ago
- An FPGA accelerator for general-purpose Sparse-Matrix Dense-Matrix Multiplication (SpMM).☆87Updated last year
- A toolchain for rapid design space exploration of chiplet architectures☆61Updated 3 months ago
- ☆16Updated 3 years ago
- ☆32Updated 11 months ago
- DAC'22 paper: "Automated Accelerator Optimization Aided by Graph Neural Networks"☆40Updated 2 years ago
- HLSFactory: A Framework Empowering High-Level Synthesis Datasets for Machine Learning and Beyond☆44Updated this week
- An Open-Source Analytical Placer for Large Scale Heterogeneous FPGAs using Deep-Learning Toolkit☆85Updated 5 months ago
- A list of our chiplet simulaters☆43Updated 4 months ago
- ☆50Updated 3 months ago
- Dynamically Reconfigurable Architecture Template and Cycle-level Microarchitecture Simulator for Dataflow AcCelerators☆30Updated 2 years ago
- CGRA-Flow is an integrated framework for CGRA compilation, exploration, synthesis, and development.☆138Updated 4 months ago
- Collection of digital hardware modules & projects (benchmarks)☆65Updated this week
- ☆60Updated 7 months ago
- High-Performance Sparse Linear Algebra on HBM-Equipped FPGAs Using HLS☆95Updated last year
- A systolic array simulator for multi-cycle MACs and varying-byte words, with the paper accepted to HPCA 2022.☆81Updated 3 years ago
- An Open-Source Tool for CGRA Accelerators☆74Updated last month
- An MLIR dialect to enable the efficient acceleration of ML model on CGRAs.☆64Updated last year
- MAERI: A DNN accelerator with reconfigurable interconnects to support flexible dataflow (http://synergy.ece.gatech.edu/tools/maeri/)☆66Updated 4 years ago
- ☆44Updated last year
- AMF-Placer 2.0: An open-source timing-driven analytical mixed-size FPGA placer of heterogeneous resources (LUT/FF/LUTRAM/MUX/CARRY/DSP/BR…☆105Updated last year
- PANDA: Architecture-Level Power Evaluation by Unifying Analytical and Machine Learning Solutions☆16Updated last year
- TAPA compiles task-parallel HLS program into high-performance FPGA accelerators.☆175Updated 2 months ago