UT-LCA / ML4Accel-DatasetLinks
Dataset for ML-guided Accelerator Design
☆37Updated 8 months ago
Alternatives and similar repositories for ML4Accel-Dataset
Users that are interested in ML4Accel-Dataset are comparing it to the libraries listed below
Sorting:
- High-Level Synthesis Performance Prediction using GNNs: Benchmarking, Modeling, and Advancing☆51Updated last year
- An integrated CGRA design framework☆90Updated 4 months ago
- [DATE 2022] PowerGear: Early-Stage Power Estimation in FPGA HLS via Heterogeneous Edge-Centric GNNs☆18Updated 3 years ago
- The open-sourced version of BOOM-Explorer☆43Updated 2 years ago
- Template-based Reconfigurable Architecture Modeling Framework☆14Updated 2 years ago
- An Open-Source Analytical Placer for Large Scale Heterogeneous FPGAs using Deep-Learning Toolkit☆82Updated 3 months ago
- A list of our chiplet simulaters☆33Updated last month
- A fast, accurate trace-based simulator for High-Level Synthesis.☆67Updated 4 months ago
- MasterRTL: A Pre-Synthesis PPA Estimation Framework for Any RTL Design☆50Updated 2 months ago
- High-Performance Sparse Linear Algebra on HBM-Equipped FPGAs Using HLS☆94Updated 10 months ago
- ☆43Updated 10 months ago
- HLSFactory: A Framework Empowering High-Level Synthesis Datasets for Machine Learning and Beyond☆39Updated 3 weeks ago
- CGRA Compilation Framework☆84Updated 2 years ago
- Collection of digital hardware modules & projects (benchmarks)☆59Updated last week
- A toolchain for rapid design space exploration of chiplet architectures☆55Updated last week
- CGRA-Flow is an integrated framework for CGRA compilation, exploration, synthesis, and development.☆135Updated last month
- ☆56Updated 4 months ago
- An MLIR dialect to enable the efficient acceleration of ML model on CGRAs.☆60Updated 9 months ago
- The RAD flow is an open-source academic architecture exploration and evaluation flow for novel beyond-FPGA reconfigurable acceleration de…☆38Updated 2 weeks ago
- ☆47Updated last month
- ☆60Updated 3 months ago
- A systolic array simulator for multi-cycle MACs and varying-byte words, with the paper accepted to HPCA 2022.☆80Updated 3 years ago
- ☆16Updated 3 years ago
- An Open-Source Tool for CGRA Accelerators☆67Updated 3 months ago
- AMF-Placer 2.0: An open-source timing-driven analytical mixed-size FPGA placer of heterogeneous resources (LUT/FF/LUTRAM/MUX/CARRY/DSP/BR…☆105Updated last year
- [FPGA 2021, Best Paper Award] An automated floorplanning and pipelining tool for Vivado HLS.☆122Updated 2 years ago
- An FPGA accelerator for general-purpose Sparse-Matrix Dense-Matrix Multiplication (SpMM).☆81Updated last year
- A dataflow architecture for universal graph neural network inference via multi-queue streaming.☆73Updated 2 years ago
- Gamora: Graph Learning based Symbolic Reasoning for Large-Scale Boolean Networks (DAC'23)☆49Updated 6 months ago
- ☆30Updated 9 months ago